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The HW supports only storing 15 keys at a time. This limits the number
of tfms that can work without failutes. Reserve keyslots to solve this
and use the reserved ones during the encryption/decryption operation.
This allow users to have the capability of hardware protected keys
and faster operations if there are limited number of tfms while not
halting the operation if there are more tfms.
Fixes: 0880bb3b00
("crypto: tegra - Add Tegra Security Engine driver")
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
179 lines
4.4 KiB
C
179 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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/*
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* Crypto driver file to manage keys of NVIDIA Security Engine.
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*/
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#include <linux/bitops.h>
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#include <linux/module.h>
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#include <crypto/aes.h>
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#include "tegra-se.h"
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#define SE_KEY_FULL_MASK GENMASK(SE_MAX_KEYSLOT, 0)
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/* Reserve keyslot 0, 14, 15 */
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#define SE_KEY_RSVD_MASK (BIT(0) | BIT(14) | BIT(15))
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#define SE_KEY_VALID_MASK (SE_KEY_FULL_MASK & ~SE_KEY_RSVD_MASK)
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/* Mutex lock to guard keyslots */
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static DEFINE_MUTEX(kslt_lock);
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/* Keyslot bitmask (0 = available, 1 = in use/not available) */
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static u16 tegra_se_keyslots = SE_KEY_RSVD_MASK;
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static u16 tegra_keyslot_alloc(void)
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{
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u16 keyid;
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mutex_lock(&kslt_lock);
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/* Check if all key slots are full */
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if (tegra_se_keyslots == GENMASK(SE_MAX_KEYSLOT, 0)) {
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mutex_unlock(&kslt_lock);
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return 0;
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}
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keyid = ffz(tegra_se_keyslots);
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tegra_se_keyslots |= BIT(keyid);
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mutex_unlock(&kslt_lock);
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return keyid;
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}
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static void tegra_keyslot_free(u16 slot)
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{
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mutex_lock(&kslt_lock);
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tegra_se_keyslots &= ~(BIT(slot));
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mutex_unlock(&kslt_lock);
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}
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static unsigned int tegra_key_prep_ins_cmd(struct tegra_se *se, u32 *cpuvaddr,
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const u32 *key, u32 keylen, u16 slot, u32 alg)
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{
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int i = 0, j;
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cpuvaddr[i++] = host1x_opcode_setpayload(1);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->op);
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cpuvaddr[i++] = SE_AES_OP_WRSTALL | SE_AES_OP_DUMMY;
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cpuvaddr[i++] = host1x_opcode_setpayload(1);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->manifest);
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cpuvaddr[i++] = se->manifest(se->owner, alg, keylen);
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cpuvaddr[i++] = host1x_opcode_setpayload(1);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->key_dst);
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cpuvaddr[i++] = SE_AES_KEY_DST_INDEX(slot);
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for (j = 0; j < keylen / 4; j++) {
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/* Set key address */
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cpuvaddr[i++] = host1x_opcode_setpayload(1);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->key_addr);
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cpuvaddr[i++] = j;
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/* Set key data */
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cpuvaddr[i++] = host1x_opcode_setpayload(1);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->key_data);
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cpuvaddr[i++] = key[j];
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}
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cpuvaddr[i++] = host1x_opcode_setpayload(1);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->config);
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cpuvaddr[i++] = SE_CFG_INS;
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cpuvaddr[i++] = host1x_opcode_setpayload(1);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->op);
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cpuvaddr[i++] = SE_AES_OP_WRSTALL | SE_AES_OP_START |
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SE_AES_OP_LASTBUF;
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cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
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cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
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host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
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dev_dbg(se->dev, "key-slot %u key-manifest %#x\n",
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slot, se->manifest(se->owner, alg, keylen));
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return i;
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}
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static bool tegra_key_in_kslt(u32 keyid)
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{
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bool ret;
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if (keyid > SE_MAX_KEYSLOT)
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return false;
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mutex_lock(&kslt_lock);
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ret = ((BIT(keyid) & SE_KEY_VALID_MASK) &&
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(BIT(keyid) & tegra_se_keyslots));
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mutex_unlock(&kslt_lock);
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return ret;
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}
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static int tegra_key_insert(struct tegra_se *se, const u8 *key,
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u32 keylen, u16 slot, u32 alg)
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{
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const u32 *keyval = (u32 *)key;
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u32 *addr = se->keybuf->addr, size;
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int ret;
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mutex_lock(&kslt_lock);
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size = tegra_key_prep_ins_cmd(se, addr, keyval, keylen, slot, alg);
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ret = tegra_se_host1x_submit(se, se->keybuf, size);
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mutex_unlock(&kslt_lock);
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return ret;
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}
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void tegra_key_invalidate(struct tegra_se *se, u32 keyid, u32 alg)
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{
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u8 zkey[AES_MAX_KEY_SIZE] = {0};
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if (!keyid)
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return;
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/* Overwrite the key with 0s */
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tegra_key_insert(se, zkey, AES_MAX_KEY_SIZE, keyid, alg);
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tegra_keyslot_free(keyid);
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}
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void tegra_key_invalidate_reserved(struct tegra_se *se, u32 keyid, u32 alg)
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{
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u8 zkey[AES_MAX_KEY_SIZE] = {0};
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if (!keyid)
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return;
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/* Overwrite the key with 0s */
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tegra_key_insert(se, zkey, AES_MAX_KEY_SIZE, keyid, alg);
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}
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inline int tegra_key_submit_reserved(struct tegra_se *se, const u8 *key,
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u32 keylen, u32 alg, u32 *keyid)
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{
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return tegra_key_insert(se, key, keylen, *keyid, alg);
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}
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int tegra_key_submit(struct tegra_se *se, const u8 *key, u32 keylen, u32 alg, u32 *keyid)
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{
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int ret;
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/* Use the existing slot if it is already allocated */
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if (!tegra_key_in_kslt(*keyid)) {
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*keyid = tegra_keyslot_alloc();
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if (!(*keyid)) {
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dev_dbg(se->dev, "failed to allocate key slot\n");
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return -ENOMEM;
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}
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}
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ret = tegra_key_insert(se, key, keylen, *keyid, alg);
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if (ret)
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return ret;
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return 0;
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}
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