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The clock tree of K1 SoC contains three main types of clock hardware (PLL/DDN/MIX) and has control registers split into several multifunction devices: APBS (PLLs), MPMU, APBC and APMU. All register operations are done through regmap to ensure atomicity between concurrent operations of clock driver and reset, power-domain driver that will be introduced in the future. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
86 lines
2 KiB
C
86 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024 SpacemiT Technology Co. Ltd
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* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
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*/
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#ifndef _CCU_PLL_H_
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#define _CCU_PLL_H_
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#include <linux/clk-provider.h>
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#include "ccu_common.h"
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/**
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* struct ccu_pll_rate_tbl - Structure mapping between PLL rate and register
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* configuration.
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*
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* @rate: PLL rate
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* @swcr1: Register value of PLLX_SW1_CTRL (PLLx_SWCR1).
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* @swcr3: Register value of the PLLx_SW3_CTRL's lowest 31 bits of
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* PLLx_SW3_CTRL (PLLx_SWCR3). This highest bit is for enabling
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* the PLL and not contained in this field.
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*/
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struct ccu_pll_rate_tbl {
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unsigned long rate;
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u32 swcr1;
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u32 swcr3;
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};
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struct ccu_pll_config {
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const struct ccu_pll_rate_tbl *rate_tbl;
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u32 tbl_num;
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u32 reg_lock;
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u32 mask_lock;
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};
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#define CCU_PLL_RATE(_rate, _swcr1, _swcr3) \
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{ \
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.rate = _rate, \
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.swcr1 = _swcr1, \
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.swcr3 = _swcr3, \
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}
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struct ccu_pll {
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struct ccu_common common;
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struct ccu_pll_config config;
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};
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#define CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock) \
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{ \
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.rate_tbl = _table, \
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.tbl_num = ARRAY_SIZE(_table), \
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.reg_lock = (_reg_lock), \
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.mask_lock = (_mask_lock), \
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}
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#define CCU_PLL_HWINIT(_name, _flags) \
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(&(struct clk_init_data) { \
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.name = #_name, \
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.ops = &spacemit_ccu_pll_ops, \
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.parent_data = &(struct clk_parent_data) { .index = 0 }, \
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.num_parents = 1, \
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.flags = _flags, \
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})
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#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \
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_mask_lock, _flags) \
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static struct ccu_pll _name = { \
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.config = CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock), \
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.common = { \
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.reg_swcr1 = _reg_swcr1, \
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.reg_swcr3 = _reg_swcr3, \
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.hw.init = CCU_PLL_HWINIT(_name, _flags) \
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} \
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}
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static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw)
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{
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struct ccu_common *common = hw_to_ccu_common(hw);
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return container_of(common, struct ccu_pll, common);
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}
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extern const struct clk_ops spacemit_ccu_pll_ops;
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#endif
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