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1b72c59db0
The clock tree of K1 SoC contains three main types of clock hardware (PLL/DDN/MIX) and has control registers split into several multifunction devices: APBS (PLLs), MPMU, APBC and APMU. All register operations are done through regmap to ensure atomicity between concurrent operations of clock driver and reset, power-domain driver that will be introduced in the future. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024 SpacemiT Technology Co. Ltd
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* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
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*/
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#ifndef _CCU_DDN_H_
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#define _CCU_DDN_H_
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include "ccu_common.h"
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struct ccu_ddn {
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struct ccu_common common;
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unsigned int num_mask;
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unsigned int num_shift;
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unsigned int den_mask;
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unsigned int den_shift;
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};
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#define CCU_DDN_INIT(_name, _parent, _flags) \
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CLK_HW_INIT_HW(#_name, &_parent.common.hw, &spacemit_ccu_ddn_ops, _flags)
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#define CCU_DDN_DEFINE(_name, _parent, _reg_ctrl, _num_shift, _num_width, \
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_den_shift, _den_width, _flags) \
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static struct ccu_ddn _name = { \
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.common = { \
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.reg_ctrl = _reg_ctrl, \
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.hw.init = CCU_DDN_INIT(_name, _parent, _flags), \
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}, \
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.num_mask = GENMASK(_num_shift + _num_width - 1, _num_shift), \
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.num_shift = _num_shift, \
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.den_mask = GENMASK(_den_shift + _den_width - 1, _den_shift), \
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.den_shift = _den_shift, \
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}
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static inline struct ccu_ddn *hw_to_ccu_ddn(struct clk_hw *hw)
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{
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struct ccu_common *common = hw_to_ccu_common(hw);
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return container_of(common, struct ccu_ddn, common);
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}
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extern const struct clk_ops spacemit_ccu_ddn_ops;
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#endif
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