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The clock tree of K1 SoC contains three main types of clock hardware (PLL/DDN/MIX) and has control registers split into several multifunction devices: APBS (PLLs), MPMU, APBC and APMU. All register operations are done through regmap to ensure atomicity between concurrent operations of clock driver and reset, power-domain driver that will be introduced in the future. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
48 lines
889 B
C
48 lines
889 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024 SpacemiT Technology Co. Ltd
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* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
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*/
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#ifndef _CCU_COMMON_H_
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#define _CCU_COMMON_H_
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#include <linux/regmap.h>
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struct ccu_common {
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struct regmap *regmap;
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struct regmap *lock_regmap;
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union {
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/* For DDN and MIX */
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struct {
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u32 reg_ctrl;
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u32 reg_fc;
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u32 mask_fc;
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};
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/* For PLL */
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struct {
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u32 reg_swcr1;
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u32 reg_swcr3;
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};
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};
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struct clk_hw hw;
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};
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static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
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{
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return container_of(hw, struct ccu_common, hw);
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}
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#define ccu_read(c, reg) \
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({ \
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u32 tmp; \
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regmap_read((c)->regmap, (c)->reg_##reg, &tmp); \
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tmp; \
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})
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#define ccu_update(c, reg, mask, val) \
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regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val)
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#endif /* _CCU_COMMON_H_ */
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