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Recent Rockchip SoCs have a new hardware block called Native Interface Unit (NIU), which gates clocks to devices behind them. These clock gates will only have a running output clock when all of the following conditions are met: 1. the parent clock is enabled 2. the enable bit is set correctly 3. the linked clock is enabled To handle them this code registers them as a normal gate type clock, which takes care of condition 1 + 2. The linked clock is handled by using runtime PM clocks. Handling it via runtime PM requires setting up a struct device for each of these clocks with a driver attached to use the correct runtime PM operations. Thus the complete handling of these clocks has been moved into its own driver. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241211165957.94922-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
85 lines
2 KiB
C
85 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2024 Collabora Ltd.
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* Author: Sebastian Reichel <sebastian.reichel@collabora.com>
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*/
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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#include "clk.h"
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static int rk_clk_gate_link_register(struct device *dev,
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struct rockchip_clk_provider *ctx,
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struct rockchip_clk_branch *clkbr)
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{
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unsigned long flags = clkbr->flags | CLK_SET_RATE_PARENT;
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struct clk *clk;
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clk = clk_register_gate(dev, clkbr->name, clkbr->parent_names[0],
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flags, ctx->reg_base + clkbr->gate_offset,
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clkbr->gate_shift, clkbr->gate_flags,
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&ctx->lock);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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rockchip_clk_set_lookup(ctx, clk, clkbr->id);
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return 0;
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}
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static int rk_clk_gate_link_probe(struct platform_device *pdev)
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{
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struct rockchip_gate_link_platdata *pdata;
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struct device *dev = &pdev->dev;
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struct clk *linked_clk;
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int ret;
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pdata = dev_get_platdata(dev);
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if (!pdata)
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return dev_err_probe(dev, -ENODEV, "missing platform data");
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ret = devm_pm_runtime_enable(dev);
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if (ret)
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return ret;
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ret = devm_pm_clk_create(dev);
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if (ret)
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return ret;
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linked_clk = rockchip_clk_get_lookup(pdata->ctx, pdata->clkbr->linked_clk_id);
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ret = pm_clk_add_clk(dev, linked_clk);
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if (ret)
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return ret;
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ret = rk_clk_gate_link_register(dev, pdata->ctx, pdata->clkbr);
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if (ret)
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goto err;
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return 0;
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err:
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pm_clk_remove_clk(dev, linked_clk);
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return ret;
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}
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static const struct dev_pm_ops rk_clk_gate_link_pm_ops = {
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SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
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};
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static struct platform_driver rk_clk_gate_link_driver = {
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.probe = rk_clk_gate_link_probe,
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.driver = {
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.name = "rockchip-gate-link-clk",
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.pm = &rk_clk_gate_link_pm_ops,
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.suppress_bind_attrs = true,
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},
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};
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static int __init rk_clk_gate_link_drv_register(void)
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{
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return platform_driver_register(&rk_clk_gate_link_driver);
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}
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core_initcall(rk_clk_gate_link_drv_register);
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