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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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e3abdd1870
* clk-renesas: (42 commits) clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs clk: renesas: r9a09g057: Add XSPI clock/reset clk: renesas: r9a09g056: Add XSPI clock/reset clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting clk: renesas: r9a09g057: Add support for xspi mux and divider clk: renesas: r9a09g056: Add support for xspi mux and divider clk: renesas: r9a09g077: Add RIIC module clocks clk: renesas: r9a09g077: Add PLL2 and SDHI clock support clk: renesas: rzv2h: Drop redundant base pointer from pll_clk clk: renesas: r9a09g057: Add entries for the RSPIs dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock clk: renesas: rzv2h: Add missing include file clk: renesas: rzv2h: Use devm_kmemdup_array() clk: renesas: Add CPG/MSSR support to RZ/N2H SoC clk: renesas: r9a09g077: Add PCLKL core clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID ... * clk-samsung: clk: samsung: exynosautov920: add block hsi2 clock support dt-bindings: clock: exynosautov920: add hsi2 clock definitions dt-bindings: clock: exynosautov920: sort clock definitions clk: samsung: exynos850: fix a comment clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD * clk-spacemit: clk: spacemit: ccu_pll: fix error return value in recalc_rate callback reset: spacemit: add support for SpacemiT CCU resets clk: spacemit: mark K1 pll1_d8 as critical clk: spacemit: define three reset-only CCUs clk: spacemit: set up reset auxiliary devices soc: spacemit: create a header for clock/reset registers dt-bindings: soc: spacemit: define spacemit,k1-ccu resets * clk-allwinner: clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate() clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll clk: sunxi-ng: v3s: Fix de clock definition clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset * clk-amlogic: clk: amlogic: s4: remove unused data clk: amlogic: drop clk_regmap tables clk: amlogic: get regmap with clk_regmap_init clk: amlogic: remove unnecessary headers clk: amlogic: axg-audio: use the auxiliary reset driver |
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|---|---|---|
| .. | ||
| a1-peripherals.c | ||
| a1-pll.c | ||
| axg-aoclk.c | ||
| axg-audio.c | ||
| axg.c | ||
| c3-peripherals.c | ||
| c3-pll.c | ||
| clk-cpu-dyndiv.c | ||
| clk-cpu-dyndiv.h | ||
| clk-dualdiv.c | ||
| clk-dualdiv.h | ||
| clk-mpll.c | ||
| clk-mpll.h | ||
| clk-phase.c | ||
| clk-phase.h | ||
| clk-pll.c | ||
| clk-pll.h | ||
| clk-regmap.c | ||
| clk-regmap.h | ||
| g12a-aoclk.c | ||
| g12a.c | ||
| gxbb-aoclk.c | ||
| gxbb.c | ||
| Kconfig | ||
| Makefile | ||
| meson-aoclk.c | ||
| meson-aoclk.h | ||
| meson-clkc-utils.c | ||
| meson-clkc-utils.h | ||
| meson-eeclk.c | ||
| meson-eeclk.h | ||
| meson8-ddr.c | ||
| meson8b.c | ||
| parm.h | ||
| s4-peripherals.c | ||
| s4-pll.c | ||
| sclk-div.c | ||
| sclk-div.h | ||
| vclk.c | ||
| vclk.h | ||
| vid-pll-div.c | ||
| vid-pll-div.h | ||