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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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c7f7ddbd27
Update the min, max ranges of the PLL clocks according to the latest
datasheet to be coherent in the driver. This patch solves the issues in
configuring the clocks related to peripherals with the desired frequency
within the range.
Fixes: 33013b43e2 ("clk: at91: sam9x7: add sam9x7 pmc driver")
Suggested-by: Patrice Vilchez <Patrice.Vilchez@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Link: https://lore.kernel.org/r/20250714093512.29944-1-varshini.rajendran@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
946 lines
21 KiB
C
946 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* SAM9X7 PMC code.
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*
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* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Varshini Rajendran <varshini.rajendran@microchip.com>
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*
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/at91.h>
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#include "pmc.h"
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static DEFINE_SPINLOCK(pmc_pll_lock);
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static DEFINE_SPINLOCK(mck_lock);
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/**
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* enum pll_ids - PLL clocks identifiers
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* @PLL_ID_PLLA: PLLA identifier
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* @PLL_ID_UPLL: UPLL identifier
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* @PLL_ID_AUDIO: Audio PLL identifier
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* @PLL_ID_LVDS: LVDS PLL identifier
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* @PLL_ID_PLLA_DIV2: PLLA DIV2 identifier
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* @PLL_ID_MAX: Max PLL Identifier
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*/
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enum pll_ids {
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PLL_ID_PLLA,
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PLL_ID_UPLL,
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PLL_ID_AUDIO,
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PLL_ID_LVDS,
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PLL_ID_PLLA_DIV2,
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PLL_ID_MAX,
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};
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/**
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* enum pll_type - PLL type identifiers
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* @PLL_TYPE_FRAC: fractional PLL identifier
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* @PLL_TYPE_DIV: divider PLL identifier
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*/
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enum pll_type {
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PLL_TYPE_FRAC,
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PLL_TYPE_DIV,
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};
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static const struct clk_master_characteristics mck_characteristics = {
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.output = { .min = 32000000, .max = 266666667 },
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.divisors = { 1, 2, 4, 3, 5},
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.have_div3_pres = 1,
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};
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static const struct clk_master_layout sam9x7_master_layout = {
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.mask = 0x373,
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.pres_shift = 4,
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.offset = 0x28,
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};
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/* Fractional PLL core output range. */
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static const struct clk_range plla_core_outputs[] = {
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{ .min = 800000000, .max = 1600000000 },
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};
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static const struct clk_range upll_core_outputs[] = {
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{ .min = 600000000, .max = 960000000 },
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};
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static const struct clk_range lvdspll_core_outputs[] = {
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{ .min = 600000000, .max = 1200000000 },
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};
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static const struct clk_range audiopll_core_outputs[] = {
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{ .min = 600000000, .max = 1200000000 },
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};
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static const struct clk_range plladiv2_core_outputs[] = {
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{ .min = 800000000, .max = 1600000000 },
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};
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/* Fractional PLL output range. */
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static const struct clk_range plla_outputs[] = {
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{ .min = 400000000, .max = 800000000 },
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};
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static const struct clk_range upll_outputs[] = {
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{ .min = 300000000, .max = 480000000 },
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};
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static const struct clk_range lvdspll_outputs[] = {
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{ .min = 175000000, .max = 550000000 },
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};
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static const struct clk_range audiopll_outputs[] = {
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{ .min = 0, .max = 300000000 },
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};
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static const struct clk_range plladiv2_outputs[] = {
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{ .min = 200000000, .max = 400000000 },
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};
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/* PLL characteristics. */
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static const struct clk_pll_characteristics plla_characteristics = {
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.input = { .min = 20000000, .max = 50000000 },
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.num_output = ARRAY_SIZE(plla_outputs),
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.output = plla_outputs,
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.core_output = plla_core_outputs,
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};
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static const struct clk_pll_characteristics upll_characteristics = {
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.input = { .min = 20000000, .max = 50000000 },
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.num_output = ARRAY_SIZE(upll_outputs),
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.output = upll_outputs,
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.core_output = upll_core_outputs,
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.upll = true,
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};
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static const struct clk_pll_characteristics lvdspll_characteristics = {
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.input = { .min = 20000000, .max = 50000000 },
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.num_output = ARRAY_SIZE(lvdspll_outputs),
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.output = lvdspll_outputs,
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.core_output = lvdspll_core_outputs,
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};
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static const struct clk_pll_characteristics audiopll_characteristics = {
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.input = { .min = 20000000, .max = 50000000 },
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.num_output = ARRAY_SIZE(audiopll_outputs),
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.output = audiopll_outputs,
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.core_output = audiopll_core_outputs,
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};
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static const struct clk_pll_characteristics plladiv2_characteristics = {
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.input = { .min = 20000000, .max = 50000000 },
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.num_output = ARRAY_SIZE(plladiv2_outputs),
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.output = plladiv2_outputs,
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.core_output = plladiv2_core_outputs,
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};
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/* Layout for fractional PLL ID PLLA. */
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static const struct clk_pll_layout plla_frac_layout = {
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.mul_mask = GENMASK(31, 24),
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.frac_mask = GENMASK(21, 0),
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.mul_shift = 24,
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.frac_shift = 0,
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.div2 = 1,
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};
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/* Layout for fractional PLLs. */
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static const struct clk_pll_layout pll_frac_layout = {
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.mul_mask = GENMASK(31, 24),
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.frac_mask = GENMASK(21, 0),
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.mul_shift = 24,
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.frac_shift = 0,
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};
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/* Layout for DIV PLLs. */
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static const struct clk_pll_layout pll_divpmc_layout = {
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.div_mask = GENMASK(7, 0),
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.endiv_mask = BIT(29),
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.div_shift = 0,
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.endiv_shift = 29,
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};
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/* Layout for DIV PLL ID PLLADIV2. */
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static const struct clk_pll_layout plladiv2_divpmc_layout = {
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.div_mask = GENMASK(7, 0),
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.endiv_mask = BIT(29),
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.div_shift = 0,
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.endiv_shift = 29,
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.div2 = 1,
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};
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/* Layout for DIVIO dividers. */
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static const struct clk_pll_layout pll_divio_layout = {
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.div_mask = GENMASK(19, 12),
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.endiv_mask = BIT(30),
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.div_shift = 12,
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.endiv_shift = 30,
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};
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/*
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* PLL clocks description
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* @n: clock name
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* @p: clock parent
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* @l: clock layout
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* @t: clock type
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* @c: pll characteristics
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* @f: clock flags
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* @eid: export index in sam9x7->chws[] array
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*/
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static const struct {
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const char *n;
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const char *p;
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const struct clk_pll_layout *l;
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u8 t;
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const struct clk_pll_characteristics *c;
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unsigned long f;
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u8 eid;
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} sam9x7_plls[][3] = {
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[PLL_ID_PLLA] = {
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{
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.n = "plla_fracck",
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.p = "mainck",
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.l = &plla_frac_layout,
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.t = PLL_TYPE_FRAC,
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/*
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* This feeds plla_divpmcck which feeds CPU. It should
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* not be disabled.
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*/
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.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
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.c = &plla_characteristics,
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},
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{
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.n = "plla_divpmcck",
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.p = "plla_fracck",
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.l = &pll_divpmc_layout,
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.t = PLL_TYPE_DIV,
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/* This feeds CPU. It should not be disabled */
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.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
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.eid = PMC_PLLACK,
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.c = &plla_characteristics,
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},
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},
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[PLL_ID_UPLL] = {
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{
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.n = "upll_fracck",
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.p = "main_osc",
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.l = &pll_frac_layout,
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.t = PLL_TYPE_FRAC,
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.f = CLK_SET_RATE_GATE,
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.c = &upll_characteristics,
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},
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{
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.n = "upll_divpmcck",
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.p = "upll_fracck",
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.l = &pll_divpmc_layout,
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.t = PLL_TYPE_DIV,
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.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT,
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.eid = PMC_UTMI,
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.c = &upll_characteristics,
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},
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},
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[PLL_ID_AUDIO] = {
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{
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.n = "audiopll_fracck",
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.p = "main_osc",
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.l = &pll_frac_layout,
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.f = CLK_SET_RATE_GATE,
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.c = &audiopll_characteristics,
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.t = PLL_TYPE_FRAC,
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},
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{
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.n = "audiopll_divpmcck",
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.p = "audiopll_fracck",
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.l = &pll_divpmc_layout,
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.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT,
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.c = &audiopll_characteristics,
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.eid = PMC_AUDIOPMCPLL,
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.t = PLL_TYPE_DIV,
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},
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{
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.n = "audiopll_diviock",
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.p = "audiopll_fracck",
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.l = &pll_divio_layout,
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.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT,
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.c = &audiopll_characteristics,
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.eid = PMC_AUDIOIOPLL,
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.t = PLL_TYPE_DIV,
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},
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},
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[PLL_ID_LVDS] = {
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{
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.n = "lvdspll_fracck",
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.p = "main_osc",
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.l = &pll_frac_layout,
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.f = CLK_SET_RATE_GATE,
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.c = &lvdspll_characteristics,
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.t = PLL_TYPE_FRAC,
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},
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{
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.n = "lvdspll_divpmcck",
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.p = "lvdspll_fracck",
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.l = &pll_divpmc_layout,
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.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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CLK_SET_RATE_PARENT,
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.c = &lvdspll_characteristics,
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.eid = PMC_LVDSPLL,
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.t = PLL_TYPE_DIV,
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},
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},
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[PLL_ID_PLLA_DIV2] = {
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{
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.n = "plla_div2pmcck",
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.p = "plla_fracck",
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.l = &plladiv2_divpmc_layout,
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/*
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* This may feed critical parts of the system like timers.
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* It should not be disabled.
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*/
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.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
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.c = &plladiv2_characteristics,
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.eid = PMC_PLLADIV2,
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.t = PLL_TYPE_DIV,
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},
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},
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};
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static const struct clk_programmable_layout sam9x7_programmable_layout = {
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.pres_mask = 0xff,
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.pres_shift = 8,
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.css_mask = 0x1f,
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.have_slck_mck = 0,
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.is_pres_direct = 1,
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};
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static const struct clk_pcr_layout sam9x7_pcr_layout = {
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.offset = 0x88,
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.cmd = BIT(31),
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.gckcss_mask = GENMASK(12, 8),
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.pid_mask = GENMASK(6, 0),
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};
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static const struct {
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char *n;
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char *p;
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u8 id;
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unsigned long flags;
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} sam9x7_systemck[] = {
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/*
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* ddrck feeds DDR controller and is enabled by bootloader thus we need
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* to keep it enabled in case there is no Linux consumer for it.
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*/
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{ .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
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{ .n = "uhpck", .p = "usbck", .id = 6 },
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{ .n = "pck0", .p = "prog0", .id = 8 },
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{ .n = "pck1", .p = "prog1", .id = 9 },
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};
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/*
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* Peripheral clocks description
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* @n: clock name
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* @f: clock flags
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* @id: peripheral id
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*/
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static const struct {
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char *n;
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unsigned long f;
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u8 id;
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} sam9x7_periphck[] = {
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{ .n = "pioA_clk", .id = 2, },
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{ .n = "pioB_clk", .id = 3, },
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{ .n = "pioC_clk", .id = 4, },
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{ .n = "flex0_clk", .id = 5, },
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{ .n = "flex1_clk", .id = 6, },
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{ .n = "flex2_clk", .id = 7, },
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{ .n = "flex3_clk", .id = 8, },
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{ .n = "flex6_clk", .id = 9, },
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{ .n = "flex7_clk", .id = 10, },
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{ .n = "flex8_clk", .id = 11, },
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{ .n = "sdmmc0_clk", .id = 12, },
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{ .n = "flex4_clk", .id = 13, },
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{ .n = "flex5_clk", .id = 14, },
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{ .n = "flex9_clk", .id = 15, },
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{ .n = "flex10_clk", .id = 16, },
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{ .n = "tcb0_clk", .id = 17, },
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{ .n = "pwm_clk", .id = 18, },
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{ .n = "adc_clk", .id = 19, },
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{ .n = "dma0_clk", .id = 20, },
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{ .n = "uhphs_clk", .id = 22, },
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{ .n = "udphs_clk", .id = 23, },
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{ .n = "macb0_clk", .id = 24, },
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{ .n = "lcd_clk", .id = 25, },
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{ .n = "sdmmc1_clk", .id = 26, },
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{ .n = "ssc_clk", .id = 28, },
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{ .n = "can0_clk", .id = 29, },
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{ .n = "can1_clk", .id = 30, },
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{ .n = "flex11_clk", .id = 32, },
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{ .n = "flex12_clk", .id = 33, },
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{ .n = "i2s_clk", .id = 34, },
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{ .n = "qspi_clk", .id = 35, },
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{ .n = "gfx2d_clk", .id = 36, },
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{ .n = "pit64b0_clk", .id = 37, },
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{ .n = "trng_clk", .id = 38, },
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{ .n = "aes_clk", .id = 39, },
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{ .n = "tdes_clk", .id = 40, },
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{ .n = "sha_clk", .id = 41, },
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{ .n = "classd_clk", .id = 42, },
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{ .n = "isi_clk", .id = 43, },
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{ .n = "pioD_clk", .id = 44, },
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{ .n = "tcb1_clk", .id = 45, },
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{ .n = "dbgu_clk", .id = 47, },
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/*
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* mpddr_clk feeds DDR controller and is enabled by bootloader thus we
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* need to keep it enabled in case there is no Linux consumer for it.
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*/
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{ .n = "mpddr_clk", .id = 49, .f = CLK_IS_CRITICAL },
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{ .n = "csi2dc_clk", .id = 52, },
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{ .n = "csi4l_clk", .id = 53, },
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{ .n = "dsi4l_clk", .id = 54, },
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{ .n = "lvdsc_clk", .id = 56, },
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{ .n = "pit64b1_clk", .id = 58, },
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{ .n = "puf_clk", .id = 59, },
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{ .n = "gmactsu_clk", .id = 67, },
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};
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/*
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* Generic clock description
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* @n: clock name
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* @pp: PLL parents
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* @pp_mux_table: PLL parents mux table
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* @r: clock output range
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* @pp_chg_id: id in parent array of changeable PLL parent
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* @pp_count: PLL parents count
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* @id: clock id
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*/
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static const struct {
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const char *n;
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const char *pp[8];
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const char pp_mux_table[8];
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struct clk_range r;
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int pp_chg_id;
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u8 pp_count;
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u8 id;
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} sam9x7_gck[] = {
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{
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.n = "flex0_gclk",
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.id = 5,
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.pp = { "plla_div2pmcck", },
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.pp_mux_table = { 8, },
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.pp_count = 1,
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.pp_chg_id = INT_MIN,
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},
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{
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.n = "flex1_gclk",
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.id = 6,
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.pp = { "plla_div2pmcck", },
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.pp_mux_table = { 8, },
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.pp_count = 1,
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.pp_chg_id = INT_MIN,
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},
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{
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.n = "flex2_gclk",
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.id = 7,
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.pp = { "plla_div2pmcck", },
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.pp_mux_table = { 8, },
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.pp_count = 1,
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.pp_chg_id = INT_MIN,
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},
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{
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.n = "flex3_gclk",
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.id = 8,
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.pp = { "plla_div2pmcck", },
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.pp_mux_table = { 8, },
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.pp_count = 1,
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.pp_chg_id = INT_MIN,
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},
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{
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.n = "flex6_gclk",
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.id = 9,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "flex7_gclk",
|
|
.id = 10,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "flex8_gclk",
|
|
.id = 11,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "sdmmc0_gclk",
|
|
.id = 12,
|
|
.r = { .max = 105000000 },
|
|
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 6, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "flex4_gclk",
|
|
.id = 13,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "flex5_gclk",
|
|
.id = 14,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "flex9_gclk",
|
|
.id = 15,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "flex10_gclk",
|
|
.id = 16,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "tcb0_gclk",
|
|
.id = 17,
|
|
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 6, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "adc_gclk",
|
|
.id = 19,
|
|
.pp = { "upll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 5, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "lcd_gclk",
|
|
.id = 25,
|
|
.r = { .max = 75000000 },
|
|
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 6, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "sdmmc1_gclk",
|
|
.id = 26,
|
|
.r = { .max = 105000000 },
|
|
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 6, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "mcan0_gclk",
|
|
.id = 29,
|
|
.r = { .max = 80000000 },
|
|
.pp = { "upll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 5, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "mcan1_gclk",
|
|
.id = 30,
|
|
.r = { .max = 80000000 },
|
|
.pp = { "upll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 5, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "flex11_gclk",
|
|
.id = 32,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "flex12_gclk",
|
|
.id = 33,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "i2s_gclk",
|
|
.id = 34,
|
|
.r = { .max = 100000000 },
|
|
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 6, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "qspi_gclk",
|
|
.id = 35,
|
|
.r = { .max = 200000000 },
|
|
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 6, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "pit64b0_gclk",
|
|
.id = 37,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "classd_gclk",
|
|
.id = 42,
|
|
.r = { .max = 100000000 },
|
|
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 6, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "tcb1_gclk",
|
|
.id = 45,
|
|
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 6, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "dbgu_gclk",
|
|
.id = 47,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "mipiphy_gclk",
|
|
.id = 55,
|
|
.r = { .max = 27000000 },
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "pit64b1_gclk",
|
|
.id = 58,
|
|
.pp = { "plla_div2pmcck", },
|
|
.pp_mux_table = { 8, },
|
|
.pp_count = 1,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
|
|
{
|
|
.n = "gmac_gclk",
|
|
.id = 67,
|
|
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
|
|
.pp_mux_table = { 6, 8, },
|
|
.pp_count = 2,
|
|
.pp_chg_id = INT_MIN,
|
|
},
|
|
};
|
|
|
|
static void __init sam9x7_pmc_setup(struct device_node *np)
|
|
{
|
|
struct clk_range range = CLK_RANGE(0, 0);
|
|
const char *td_slck_name, *md_slck_name, *mainxtal_name;
|
|
struct pmc_data *sam9x7_pmc;
|
|
const char *parent_names[9];
|
|
void **clk_mux_buffer = NULL;
|
|
int clk_mux_buffer_size = 0;
|
|
struct clk_hw *main_osc_hw;
|
|
struct regmap *regmap;
|
|
struct clk_hw *hw;
|
|
int i, j;
|
|
|
|
i = of_property_match_string(np, "clock-names", "td_slck");
|
|
if (i < 0)
|
|
return;
|
|
|
|
td_slck_name = of_clk_get_parent_name(np, i);
|
|
|
|
i = of_property_match_string(np, "clock-names", "md_slck");
|
|
if (i < 0)
|
|
return;
|
|
|
|
md_slck_name = of_clk_get_parent_name(np, i);
|
|
|
|
i = of_property_match_string(np, "clock-names", "main_xtal");
|
|
if (i < 0)
|
|
return;
|
|
mainxtal_name = of_clk_get_parent_name(np, i);
|
|
|
|
regmap = device_node_to_regmap(np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
sam9x7_pmc = pmc_data_allocate(PMC_LVDSPLL + 1,
|
|
nck(sam9x7_systemck),
|
|
nck(sam9x7_periphck),
|
|
nck(sam9x7_gck), 8);
|
|
if (!sam9x7_pmc)
|
|
return;
|
|
|
|
clk_mux_buffer = kmalloc(sizeof(void *) *
|
|
(ARRAY_SIZE(sam9x7_gck)),
|
|
GFP_KERNEL);
|
|
if (!clk_mux_buffer)
|
|
goto err_free;
|
|
|
|
hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
|
|
50000000);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
main_osc_hw = hw;
|
|
|
|
parent_names[0] = "main_rc_osc";
|
|
parent_names[1] = "main_osc";
|
|
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
sam9x7_pmc->chws[PMC_MAIN] = hw;
|
|
|
|
for (i = 0; i < PLL_ID_MAX; i++) {
|
|
for (j = 0; j < 3; j++) {
|
|
struct clk_hw *parent_hw;
|
|
|
|
if (!sam9x7_plls[i][j].n)
|
|
continue;
|
|
|
|
switch (sam9x7_plls[i][j].t) {
|
|
case PLL_TYPE_FRAC:
|
|
if (!strcmp(sam9x7_plls[i][j].p, "mainck"))
|
|
parent_hw = sam9x7_pmc->chws[PMC_MAIN];
|
|
else if (!strcmp(sam9x7_plls[i][j].p, "main_osc"))
|
|
parent_hw = main_osc_hw;
|
|
else
|
|
parent_hw = __clk_get_hw(of_clk_get_by_name
|
|
(np, sam9x7_plls[i][j].p));
|
|
|
|
hw = sam9x60_clk_register_frac_pll(regmap,
|
|
&pmc_pll_lock,
|
|
sam9x7_plls[i][j].n,
|
|
sam9x7_plls[i][j].p,
|
|
parent_hw, i,
|
|
sam9x7_plls[i][j].c,
|
|
sam9x7_plls[i][j].l,
|
|
sam9x7_plls[i][j].f);
|
|
break;
|
|
|
|
case PLL_TYPE_DIV:
|
|
hw = sam9x60_clk_register_div_pll(regmap,
|
|
&pmc_pll_lock,
|
|
sam9x7_plls[i][j].n,
|
|
sam9x7_plls[i][j].p, NULL, i,
|
|
sam9x7_plls[i][j].c,
|
|
sam9x7_plls[i][j].l,
|
|
sam9x7_plls[i][j].f, 0);
|
|
break;
|
|
|
|
default:
|
|
continue;
|
|
}
|
|
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
if (sam9x7_plls[i][j].eid)
|
|
sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw;
|
|
}
|
|
}
|
|
|
|
parent_names[0] = md_slck_name;
|
|
parent_names[1] = "mainck";
|
|
parent_names[2] = "plla_divpmcck";
|
|
parent_names[3] = "upll_divpmcck";
|
|
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
|
|
parent_names, NULL, &sam9x7_master_layout,
|
|
&mck_characteristics, &mck_lock);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
hw = at91_clk_register_master_div(regmap, "masterck_div",
|
|
"masterck_pres", NULL, &sam9x7_master_layout,
|
|
&mck_characteristics, &mck_lock,
|
|
CLK_SET_RATE_GATE, 0);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
sam9x7_pmc->chws[PMC_MCK] = hw;
|
|
|
|
parent_names[0] = "plla_divpmcck";
|
|
parent_names[1] = "upll_divpmcck";
|
|
parent_names[2] = "main_osc";
|
|
hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
parent_names[0] = md_slck_name;
|
|
parent_names[1] = td_slck_name;
|
|
parent_names[2] = "mainck";
|
|
parent_names[3] = "masterck_div";
|
|
parent_names[4] = "plla_divpmcck";
|
|
parent_names[5] = "upll_divpmcck";
|
|
parent_names[6] = "audiopll_divpmcck";
|
|
for (i = 0; i < 2; i++) {
|
|
char name[6];
|
|
|
|
snprintf(name, sizeof(name), "prog%d", i);
|
|
|
|
hw = at91_clk_register_programmable(regmap, name,
|
|
parent_names, NULL, 7, i,
|
|
&sam9x7_programmable_layout,
|
|
NULL);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
sam9x7_pmc->pchws[i] = hw;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) {
|
|
hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n,
|
|
sam9x7_systemck[i].p, NULL,
|
|
sam9x7_systemck[i].id,
|
|
sam9x7_systemck[i].flags);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) {
|
|
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
|
|
&sam9x7_pcr_layout,
|
|
sam9x7_periphck[i].n,
|
|
"masterck_div", NULL,
|
|
sam9x7_periphck[i].id,
|
|
&range, INT_MIN,
|
|
sam9x7_periphck[i].f);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw;
|
|
}
|
|
|
|
parent_names[0] = md_slck_name;
|
|
parent_names[1] = td_slck_name;
|
|
parent_names[2] = "mainck";
|
|
parent_names[3] = "masterck_div";
|
|
for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) {
|
|
u8 num_parents = 4 + sam9x7_gck[i].pp_count;
|
|
u32 *mux_table;
|
|
|
|
mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
|
|
GFP_KERNEL);
|
|
if (!mux_table)
|
|
goto err_free;
|
|
|
|
PMC_INIT_TABLE(mux_table, 4);
|
|
PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table,
|
|
sam9x7_gck[i].pp_count);
|
|
PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp,
|
|
sam9x7_gck[i].pp_count);
|
|
|
|
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
|
|
&sam9x7_pcr_layout,
|
|
sam9x7_gck[i].n,
|
|
parent_names, NULL, mux_table,
|
|
num_parents,
|
|
sam9x7_gck[i].id,
|
|
&sam9x7_gck[i].r,
|
|
sam9x7_gck[i].pp_chg_id);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw;
|
|
clk_mux_buffer[clk_mux_buffer_size++] = mux_table;
|
|
}
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc);
|
|
kfree(clk_mux_buffer);
|
|
|
|
return;
|
|
|
|
err_free:
|
|
if (clk_mux_buffer) {
|
|
for (i = 0; i < clk_mux_buffer_size; i++)
|
|
kfree(clk_mux_buffer[i]);
|
|
kfree(clk_mux_buffer);
|
|
}
|
|
kfree(sam9x7_pmc);
|
|
}
|
|
|
|
/* Some clks are used for a clocksource */
|
|
CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup);
|