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0c6176e1e1
Enable the driver to show all supported error injections for EINJ and EINJv2 at the same time. EINJv2 capabilities can be discovered by checking the return value of get_error_type, where bit 30 set indicates EINJv2 support. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Zaid Alali <zaidal@os.amperecomputing.com> Link: https://patch.msgid.link/20250617193026.637510-3-zaidal@os.amperecomputing.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* CXL Error INJection support. Used by CXL core to inject
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* protocol errors into CXL ports.
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*
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* Copyright (C) 2023 Advanced Micro Devices, Inc.
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*
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* Author: Ben Cheatham <benjamin.cheatham@amd.com>
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*/
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#include <linux/seq_file.h>
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#include <linux/pci.h>
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#include <cxl/einj.h>
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#include "apei-internal.h"
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/* Defined in einj-core.c */
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extern bool einj_initialized;
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static struct { u32 mask; const char *str; } const einj_cxl_error_type_string[] = {
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{ ACPI_EINJ_CXL_CACHE_CORRECTABLE, "CXL.cache Protocol Correctable" },
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{ ACPI_EINJ_CXL_CACHE_UNCORRECTABLE, "CXL.cache Protocol Uncorrectable non-fatal" },
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{ ACPI_EINJ_CXL_CACHE_FATAL, "CXL.cache Protocol Uncorrectable fatal" },
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{ ACPI_EINJ_CXL_MEM_CORRECTABLE, "CXL.mem Protocol Correctable" },
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{ ACPI_EINJ_CXL_MEM_UNCORRECTABLE, "CXL.mem Protocol Uncorrectable non-fatal" },
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{ ACPI_EINJ_CXL_MEM_FATAL, "CXL.mem Protocol Uncorrectable fatal" },
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};
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int einj_cxl_available_error_type_show(struct seq_file *m, void *v)
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{
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int cxl_err, rc;
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u32 available_error_type = 0;
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rc = einj_get_available_error_type(&available_error_type, ACPI_EINJ_GET_ERROR_TYPE);
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if (rc)
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return rc;
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for (int pos = 0; pos < ARRAY_SIZE(einj_cxl_error_type_string); pos++) {
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cxl_err = ACPI_EINJ_CXL_CACHE_CORRECTABLE << pos;
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if (available_error_type & cxl_err)
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seq_printf(m, "0x%08x\t%s\n",
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einj_cxl_error_type_string[pos].mask,
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einj_cxl_error_type_string[pos].str);
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}
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(einj_cxl_available_error_type_show, "CXL");
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static int cxl_dport_get_sbdf(struct pci_dev *dport_dev, u64 *sbdf)
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{
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struct pci_bus *pbus;
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struct pci_host_bridge *bridge;
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u64 seg = 0, bus;
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pbus = dport_dev->bus;
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bridge = pci_find_host_bridge(pbus);
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if (!bridge)
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return -ENODEV;
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if (bridge->domain_nr != PCI_DOMAIN_NR_NOT_SET)
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seg = bridge->domain_nr;
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bus = pbus->number;
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*sbdf = (seg << 24) | (bus << 16) | (dport_dev->devfn << 8);
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return 0;
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}
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int einj_cxl_inject_rch_error(u64 rcrb, u64 type)
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{
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int rc;
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/* Only CXL error types can be specified */
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if (!einj_is_cxl_error_type(type))
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return -EINVAL;
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rc = einj_validate_error_type(type);
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if (rc)
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return rc;
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return einj_cxl_rch_error_inject(type, 0x2, rcrb, GENMASK_ULL(63, 0),
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0, 0);
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}
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EXPORT_SYMBOL_NS_GPL(einj_cxl_inject_rch_error, "CXL");
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int einj_cxl_inject_error(struct pci_dev *dport, u64 type)
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{
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u64 param4 = 0;
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int rc;
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/* Only CXL error types can be specified */
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if (!einj_is_cxl_error_type(type))
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return -EINVAL;
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rc = einj_validate_error_type(type);
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if (rc)
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return rc;
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rc = cxl_dport_get_sbdf(dport, ¶m4);
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if (rc)
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return rc;
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return einj_error_inject(type, 0x4, 0, 0, 0, param4);
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}
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EXPORT_SYMBOL_NS_GPL(einj_cxl_inject_error, "CXL");
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bool einj_cxl_is_initialized(void)
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{
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return einj_initialized;
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}
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EXPORT_SYMBOL_NS_GPL(einj_cxl_is_initialized, "CXL");
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