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f4d7b8a6bc
Add SET_STATE ioctl to configure device power mode for aie2 device. Three modes are supported initially. POWER_MODE_DEFAULT: Enable clock gating and set DPM (Dynamic Power Management) level to value which has been set by resource solver or maximum DPM level the device supports. POWER_MODE_HIGH: Enable clock gating and set DPM level to maximum DPM level the device supports. POWER_MODE_TURBO: Disable clock gating and set DPM level to maximum DPM level the device supports. Disabling clock gating means all clocks always run on full speed. And the different clock frequency are used based on DPM level been set. Initially, the driver set the power mode to default mode. Co-developed-by: Narendra Gutta <VenkataNarendraKumar.Gutta@amd.com> Signed-off-by: Narendra Gutta <VenkataNarendraKumar.Gutta@amd.com> Co-developed-by: George Yang <George.Yang@amd.com> Signed-off-by: George Yang <George.Yang@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213232933.1545388-4-lizhi.hou@amd.com
108 lines
2.1 KiB
C
108 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024, Advanced Micro Devices, Inc.
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*/
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#include <drm/amdxdna_accel.h>
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#include <drm/drm_device.h>
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#include <drm/drm_print.h>
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#include <drm/gpu_scheduler.h>
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#include "aie2_pci.h"
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#include "amdxdna_pci_drv.h"
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#define AIE2_CLK_GATING_ENABLE 1
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#define AIE2_CLK_GATING_DISABLE 0
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static int aie2_pm_set_clk_gating(struct amdxdna_dev_hdl *ndev, u32 val)
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{
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int ret;
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ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_CLK_GATING, &val);
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if (ret)
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return ret;
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ndev->clk_gating = val;
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return 0;
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}
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int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
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{
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int ret;
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if (ndev->dev_status != AIE2_DEV_UNINIT) {
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/* Resume device */
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ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->dpm_level);
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if (ret)
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return ret;
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ret = aie2_pm_set_clk_gating(ndev, ndev->clk_gating);
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if (ret)
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return ret;
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return 0;
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}
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while (ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk)
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ndev->max_dpm_level++;
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ndev->max_dpm_level--;
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ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->max_dpm_level);
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if (ret)
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return ret;
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ret = aie2_pm_set_clk_gating(ndev, AIE2_CLK_GATING_ENABLE);
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if (ret)
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return ret;
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ndev->pw_mode = POWER_MODE_DEFAULT;
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ndev->dft_dpm_level = ndev->max_dpm_level;
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return 0;
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}
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int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target)
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{
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struct amdxdna_dev *xdna = ndev->xdna;
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u32 clk_gating, dpm_level;
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int ret;
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drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
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if (ndev->pw_mode == target)
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return 0;
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switch (target) {
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case POWER_MODE_TURBO:
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if (ndev->hwctx_num) {
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XDNA_ERR(xdna, "Can not set turbo when there is active hwctx");
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return -EINVAL;
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}
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clk_gating = AIE2_CLK_GATING_DISABLE;
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dpm_level = ndev->max_dpm_level;
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break;
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case POWER_MODE_HIGH:
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clk_gating = AIE2_CLK_GATING_ENABLE;
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dpm_level = ndev->max_dpm_level;
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break;
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case POWER_MODE_DEFAULT:
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clk_gating = AIE2_CLK_GATING_ENABLE;
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dpm_level = ndev->dft_dpm_level;
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break;
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default:
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return -EOPNOTSUPP;
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}
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ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level);
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if (ret)
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return ret;
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ret = aie2_pm_set_clk_gating(ndev, clk_gating);
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if (ret)
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return ret;
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ndev->pw_mode = target;
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return 0;
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}
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