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Resctrl is a filesystem interface to hardware that provides cache allocation policy and bandwidth control for groups of tasks or CPUs. To support more than one architecture, resctrl needs to live in /fs/. Move the code that is concerned with the filesystem interface to /fs/resctrl. Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Reviewed-by: Fenghua Yu <fenghuay@nvidia.com> Tested-by: Fenghua Yu <fenghuay@nvidia.com> Tested-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/20250515165855.31452-25-james.morse@arm.com
93 lines
2.4 KiB
C
93 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Resource Director Technology(RDT)
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* - Cache Allocation code.
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*
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* Copyright (C) 2016 Intel Corporation
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*
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* Authors:
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* Fenghua Yu <fenghua.yu@intel.com>
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* Tony Luck <tony.luck@intel.com>
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*
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* More information about RDT be found in the Intel (R) x86 Architecture
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* Software Developer Manual June 2016, volume 3, section 17.17.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/cpu.h>
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#include "internal.h"
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int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain *d,
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u32 closid, enum resctrl_conf_type t, u32 cfg_val)
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{
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struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d);
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
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u32 idx = resctrl_get_config_index(closid, t);
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struct msr_param msr_param;
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if (!cpumask_test_cpu(smp_processor_id(), &d->hdr.cpu_mask))
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return -EINVAL;
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hw_dom->ctrl_val[idx] = cfg_val;
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msr_param.res = r;
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msr_param.dom = d;
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msr_param.low = idx;
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msr_param.high = idx + 1;
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hw_res->msr_update(&msr_param);
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return 0;
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}
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int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid)
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{
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struct resctrl_staged_config *cfg;
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struct rdt_hw_ctrl_domain *hw_dom;
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struct msr_param msr_param;
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struct rdt_ctrl_domain *d;
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enum resctrl_conf_type t;
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u32 idx;
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/* Walking r->domains, ensure it can't race with cpuhp */
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lockdep_assert_cpus_held();
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list_for_each_entry(d, &r->ctrl_domains, hdr.list) {
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hw_dom = resctrl_to_arch_ctrl_dom(d);
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msr_param.res = NULL;
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for (t = 0; t < CDP_NUM_TYPES; t++) {
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cfg = &hw_dom->d_resctrl.staged_config[t];
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if (!cfg->have_new_ctrl)
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continue;
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idx = resctrl_get_config_index(closid, t);
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if (cfg->new_ctrl == hw_dom->ctrl_val[idx])
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continue;
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hw_dom->ctrl_val[idx] = cfg->new_ctrl;
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if (!msr_param.res) {
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msr_param.low = idx;
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msr_param.high = msr_param.low + 1;
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msr_param.res = r;
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msr_param.dom = d;
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} else {
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msr_param.low = min(msr_param.low, idx);
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msr_param.high = max(msr_param.high, idx + 1);
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}
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}
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if (msr_param.res)
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smp_call_function_any(&d->hdr.cpu_mask, rdt_ctrl_update, &msr_param, 1);
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}
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return 0;
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}
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u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain *d,
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u32 closid, enum resctrl_conf_type type)
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{
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struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d);
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u32 idx = resctrl_get_config_index(closid, type);
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return hw_dom->ctrl_val[idx];
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}
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