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Intel Advanced Performance Extensions (APX) introduce a new set of general-purpose registers, managed as an extended state component via the xstate management facility. Before enabling this new xstate, define a feature flag to clarify the dependency in xsave_cpuid_features[]. APX is enumerated under CPUID level 7 with EDX=1. Since this CPUID leaf is not yet allocated, place the flag in a scattered feature word. While this feature is intended only for userspace, exposing it via /proc/cpuinfo is unnecessary. Instead, the existing arch_prctl(2) mechanism with the ARCH_GET_XCOMP_SUPP option can be used to query the feature availability. Finally, clarify that APX depends on XSAVE. Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/r/20250416021720.12305-2-chang.seok.bae@intel.com
189 lines
6.5 KiB
C
189 lines
6.5 KiB
C
/* Declare dependencies between CPUIDs */
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/cpufeature.h>
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struct cpuid_dep {
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unsigned int feature;
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unsigned int depends;
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};
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/*
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* Table of CPUID features that depend on others.
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*
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* This only includes dependencies that can be usefully disabled, not
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* features part of the base set (like FPU).
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*
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* Note this all is not __init / __initdata because it can be
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* called from cpu hotplug. It shouldn't do anything in this case,
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* but it's difficult to tell that to the init reference checker.
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*/
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static const struct cpuid_dep cpuid_deps[] = {
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{ X86_FEATURE_FXSR, X86_FEATURE_FPU },
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{ X86_FEATURE_XSAVEOPT, X86_FEATURE_XSAVE },
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{ X86_FEATURE_XSAVEC, X86_FEATURE_XSAVE },
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{ X86_FEATURE_XSAVES, X86_FEATURE_XSAVE },
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{ X86_FEATURE_AVX, X86_FEATURE_XSAVE },
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{ X86_FEATURE_PKU, X86_FEATURE_XSAVE },
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{ X86_FEATURE_MPX, X86_FEATURE_XSAVE },
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{ X86_FEATURE_XGETBV1, X86_FEATURE_XSAVE },
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{ X86_FEATURE_APX, X86_FEATURE_XSAVE },
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{ X86_FEATURE_CMOV, X86_FEATURE_FXSR },
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{ X86_FEATURE_MMX, X86_FEATURE_FXSR },
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{ X86_FEATURE_MMXEXT, X86_FEATURE_MMX },
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{ X86_FEATURE_FXSR_OPT, X86_FEATURE_FXSR },
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{ X86_FEATURE_XSAVE, X86_FEATURE_FXSR },
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{ X86_FEATURE_XMM, X86_FEATURE_FXSR },
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{ X86_FEATURE_XMM2, X86_FEATURE_XMM },
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{ X86_FEATURE_XMM3, X86_FEATURE_XMM2 },
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{ X86_FEATURE_XMM4_1, X86_FEATURE_XMM2 },
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{ X86_FEATURE_XMM4_2, X86_FEATURE_XMM2 },
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{ X86_FEATURE_XMM3, X86_FEATURE_XMM2 },
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{ X86_FEATURE_PCLMULQDQ, X86_FEATURE_XMM2 },
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{ X86_FEATURE_SSSE3, X86_FEATURE_XMM2, },
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{ X86_FEATURE_F16C, X86_FEATURE_XMM2, },
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{ X86_FEATURE_AES, X86_FEATURE_XMM2 },
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{ X86_FEATURE_SHA_NI, X86_FEATURE_XMM2 },
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{ X86_FEATURE_GFNI, X86_FEATURE_XMM2 },
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{ X86_FEATURE_AVX_VNNI, X86_FEATURE_AVX },
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{ X86_FEATURE_FMA, X86_FEATURE_AVX },
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{ X86_FEATURE_VAES, X86_FEATURE_AVX },
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{ X86_FEATURE_VPCLMULQDQ, X86_FEATURE_AVX },
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{ X86_FEATURE_AVX2, X86_FEATURE_AVX, },
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{ X86_FEATURE_AVX512F, X86_FEATURE_AVX, },
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{ X86_FEATURE_AVX512IFMA, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512PF, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512ER, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512CD, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512DQ, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512BW, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512VL, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512VBMI, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512_VBMI2, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_AVX512_VNNI, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_AVX512_BITALG, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_AVX512_4VNNIW, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512_4FMAPS, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512_VP2INTERSECT, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC },
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{ X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC },
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{ X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC },
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{ X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL },
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{ X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL },
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{ X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW },
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{ X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES },
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{ X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA },
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{ X86_FEATURE_SGX_LC, X86_FEATURE_SGX },
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{ X86_FEATURE_SGX1, X86_FEATURE_SGX },
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{ X86_FEATURE_SGX2, X86_FEATURE_SGX1 },
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{ X86_FEATURE_SGX_EDECCSSA, X86_FEATURE_SGX1 },
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{ X86_FEATURE_XFD, X86_FEATURE_XSAVES },
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{ X86_FEATURE_XFD, X86_FEATURE_XGETBV1 },
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{ X86_FEATURE_AMX_TILE, X86_FEATURE_XFD },
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{ X86_FEATURE_AMX_FP16, X86_FEATURE_AMX_TILE },
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{ X86_FEATURE_AMX_BF16, X86_FEATURE_AMX_TILE },
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{ X86_FEATURE_AMX_INT8, X86_FEATURE_AMX_TILE },
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{ X86_FEATURE_SHSTK, X86_FEATURE_XSAVES },
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{ X86_FEATURE_FRED, X86_FEATURE_LKGS },
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{ X86_FEATURE_SPEC_CTRL_SSBD, X86_FEATURE_SPEC_CTRL },
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{}
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};
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static inline void clear_feature(struct cpuinfo_x86 *c, unsigned int feature)
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{
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/*
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* Note: This could use the non atomic __*_bit() variants, but the
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* rest of the cpufeature code uses atomics as well, so keep it for
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* consistency. Cleanup all of it separately.
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*/
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if (!c) {
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clear_cpu_cap(&boot_cpu_data, feature);
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set_bit(feature, (unsigned long *)cpu_caps_cleared);
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} else {
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clear_bit(feature, (unsigned long *)c->x86_capability);
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}
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}
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/* Take the capabilities and the BUG bits into account */
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#define MAX_FEATURE_BITS ((NCAPINTS + NBUGINTS) * sizeof(u32) * 8)
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static void do_clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int feature)
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{
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DECLARE_BITMAP(disable, MAX_FEATURE_BITS);
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const struct cpuid_dep *d;
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bool changed;
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if (WARN_ON(feature >= MAX_FEATURE_BITS))
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return;
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if (boot_cpu_has(feature))
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WARN_ON(alternatives_patched);
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clear_feature(c, feature);
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/* Collect all features to disable, handling dependencies */
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memset(disable, 0, sizeof(disable));
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__set_bit(feature, disable);
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/* Loop until we get a stable state. */
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do {
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changed = false;
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for (d = cpuid_deps; d->feature; d++) {
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if (!test_bit(d->depends, disable))
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continue;
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if (__test_and_set_bit(d->feature, disable))
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continue;
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changed = true;
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clear_feature(c, d->feature);
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}
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} while (changed);
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}
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void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int feature)
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{
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do_clear_cpu_cap(c, feature);
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}
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void setup_clear_cpu_cap(unsigned int feature)
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{
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do_clear_cpu_cap(NULL, feature);
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}
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/*
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* Return the feature "name" if available, otherwise return
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* the X86_FEATURE_* numerals to make it easier to identify
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* the feature.
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*/
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static const char *x86_feature_name(unsigned int feature, char *buf)
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{
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if (x86_cap_flags[feature])
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return x86_cap_flags[feature];
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snprintf(buf, 16, "%d*32+%2d", feature / 32, feature % 32);
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return buf;
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}
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void check_cpufeature_deps(struct cpuinfo_x86 *c)
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{
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char feature_buf[16], depends_buf[16];
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const struct cpuid_dep *d;
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for (d = cpuid_deps; d->feature; d++) {
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if (cpu_has(c, d->feature) && !cpu_has(c, d->depends)) {
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/*
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* Only warn about the first unmet dependency on the
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* first CPU where it is encountered to avoid spamming
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* the kernel log.
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*/
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pr_warn_once("x86 CPU feature dependency check failure: CPU%d has '%s' enabled but '%s' disabled. Kernel might be fine, but no guarantees.\n",
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smp_processor_id(),
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x86_feature_name(d->feature, feature_buf),
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x86_feature_name(d->depends, depends_buf));
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}
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}
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}
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