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The x86-32 kernel used to support multiple platforms with more than eight logical CPUs, from the 1999-2003 timeframe: Sequent NUMA-Q, IBM Summit, Unisys ES7000 and HP F8. Support for all except the latter was dropped back in 2014, leaving only the F8 based DL740 and DL760 G2 machines in this catery, with up to eight single-core Socket-603 Xeon-MP processors with hyperthreading. Like the already removed machines, the HP F8 servers at the time cost upwards of $100k in typical configurations, but were quickly obsoleted by their 64-bit Socket-604 cousins and the AMD Opteron. Earlier servers with up to 8 Pentium Pro or Xeon processors remain fully supported as they had no hyperthreading. Similarly, the more common 4-socket Xeon-MP machines with hyperthreading using Intel or ServerWorks chipsets continue to work without this, and all the multi-core Xeon processors also run 64-bit kernels. While the "bigsmp" support can also be used to run on later 64-bit machines (including VM guests), it seems best to discourage that and get any remaining users to update their kernels to 64-bit builds on these. As a side-effect of this, there is also no more need to support NUMA configurations on 32-bit x86, as all true 32-bit NUMA platforms are already gone. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250226213714.4040853-3-arnd@kernel.org
68 lines
1.9 KiB
C
68 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Historical copyright notices:
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*
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* Copyright 2004 James Cleverdon, IBM.
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
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* (c) 2002,2003 Andi Kleen, SuSE Labs.
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*/
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#include <linux/jump_label.h>
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#include <asm/irq_vectors.h>
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#include <asm/apic.h>
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/* X2APIC */
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void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest);
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u32 x2apic_get_apic_id(u32 id);
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void x2apic_send_IPI_all(int vector);
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void x2apic_send_IPI_allbutself(int vector);
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void x2apic_send_IPI_self(int vector);
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extern u32 x2apic_max_apicid;
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/* IPI */
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DECLARE_STATIC_KEY_FALSE(apic_use_ipi_shorthand);
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static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector,
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unsigned int dest)
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{
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unsigned int icr = shortcut | dest;
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switch (vector) {
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default:
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icr |= APIC_DM_FIXED | vector;
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break;
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case NMI_VECTOR:
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icr |= APIC_DM_NMI;
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break;
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}
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return icr;
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}
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void default_init_apic_ldr(void);
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void apic_mem_wait_icr_idle(void);
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u32 apic_mem_wait_icr_idle_timeout(void);
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/*
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* This is used to send an IPI with no shorthand notation (the destination is
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* specified in bits 56 to 63 of the ICR).
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*/
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void __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest);
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void default_send_IPI_single(int cpu, int vector);
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void default_send_IPI_single_phys(int cpu, int vector);
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void default_send_IPI_mask_sequence_phys(const struct cpumask *mask, int vector);
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void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask, int vector);
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void default_send_IPI_allbutself(int vector);
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void default_send_IPI_all(int vector);
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void default_send_IPI_self(int vector);
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#ifdef CONFIG_X86_32
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void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, int vector);
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void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, int vector);
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void default_send_IPI_mask_logical(const struct cpumask *mask, int vector);
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#endif
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