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Starting with Zen4, AMD's Scalable MCA systems incorporate two new registers: MCA_SYND1 and MCA_SYND2. These registers will include supplemental error information in addition to the existing MCA_SYND register. The data within these registers is considered valid if MCA_STATUS[SyndV] is set. Userspace error decoding tools like rasdaemon gather related hardware error information through the tracepoints. Therefore, export these two registers through the mce_record tracepoint so that tools like rasdaemon can parse them and output the supplemental error information like FRU text contained in them. [ bp: Massage. ] Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Avadhut Naik <avadhut.naik@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://lore.kernel.org/r/20241022194158.110073-4-avadhut.naik@amd.com
46 lines
1.8 KiB
C
46 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _UAPI_ASM_X86_MCE_H
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#define _UAPI_ASM_X86_MCE_H
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#include <linux/types.h>
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#include <linux/ioctl.h>
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/*
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* Fields are zero when not available. Also, this struct is shared with
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* userspace mcelog and thus must keep existing fields at current offsets.
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* Only add new, shared fields to the end of the structure.
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* Do not add vendor-specific fields.
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*/
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struct mce {
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__u64 status; /* Bank's MCi_STATUS MSR */
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__u64 misc; /* Bank's MCi_MISC MSR */
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__u64 addr; /* Bank's MCi_ADDR MSR */
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__u64 mcgstatus; /* Machine Check Global Status MSR */
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__u64 ip; /* Instruction Pointer when the error happened */
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__u64 tsc; /* CPU time stamp counter */
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__u64 time; /* Wall time_t when error was detected */
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__u8 cpuvendor; /* Kernel's X86_VENDOR enum */
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__u8 inject_flags; /* Software inject flags */
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__u8 severity; /* Error severity */
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__u8 pad;
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__u32 cpuid; /* CPUID 1 EAX */
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__u8 cs; /* Code segment */
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__u8 bank; /* Machine check bank reporting the error */
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__u8 cpu; /* CPU number; obsoleted by extcpu */
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__u8 finished; /* Entry is valid */
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__u32 extcpu; /* Linux CPU number that detected the error */
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__u32 socketid; /* CPU socket ID */
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__u32 apicid; /* CPU initial APIC ID */
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__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
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__u64 synd; /* MCA_SYND MSR: only valid on SMCA systems */
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__u64 ipid; /* MCA_IPID MSR: only valid on SMCA systems */
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__u64 ppin; /* Protected Processor Inventory Number */
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__u32 microcode; /* Microcode revision */
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__u64 kflags; /* Internal kernel use */
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};
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#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
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#define MCE_GET_LOG_LEN _IOR('M', 2, int)
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#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
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#endif /* _UAPI_ASM_X86_MCE_H */
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