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22f4269726
Commit 43fe1abc18 ("x86/uv: Use hierarchical irqdomain to manage UV interrupts")
removed the implementation but left declaration.
Signed-off-by: Yue Haibing <yuehaibing@huawei.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240814031636.1304772-1-yuehaibing@huawei.com
37 lines
848 B
C
37 lines
848 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV IRQ definitions
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*
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* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_X86_UV_UV_IRQ_H
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#define _ASM_X86_UV_UV_IRQ_H
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/* If a generic version of this structure gets defined, eliminate this one. */
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struct uv_IO_APIC_route_entry {
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__u64 vector : 8,
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delivery_mode : 3,
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dest_mode : 1,
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delivery_status : 1,
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polarity : 1,
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__reserved_1 : 1,
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trigger : 1,
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mask : 1,
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__reserved_2 : 15,
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dest : 32;
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};
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enum {
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UV_AFFINITY_ALL,
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UV_AFFINITY_NODE,
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UV_AFFINITY_CPU
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};
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extern int uv_setup_irq(char *, int, int, unsigned long, int);
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extern void uv_teardown_irq(unsigned int);
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#endif /* _ASM_X86_UV_UV_IRQ_H */
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