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b9e53f9ff4
Add plumbing to the AMD IOMMU driver to allow KVM to control whether or not an IRTE is configured to generate GA log interrupts. KVM only needs a notification if the target vCPU is blocking, so the vCPU can be awakened. If a vCPU is preempted or exits to userspace, KVM clears is_run, but will set the vCPU back to running when userspace does KVM_RUN and/or the vCPU task is scheduled back in, i.e. KVM doesn't need a notification. Unconditionally pass "true" in all KVM paths to isolate the IOMMU changes from the KVM changes insofar as possible. Opportunistically swap the ordering of parameters for amd_iommu_update_ga() so that the match amd_iommu_activate_guest_mode(). Note, as of this writing, the AMD IOMMU manual doesn't list GALogIntr as a non-cached field, but per AMD hardware architects, it's not cached and can be safely updated without an invalidation. Link: https://lore.kernel.org/all/b29b8c22-2fd4-4b5e-b755-9198874157c7@amd.com Cc: Vasant Hegde <vasant.hegde@amd.com> Cc: Joao Martins <joao.m.martins@oracle.com> Link: https://lore.kernel.org/r/20250611224604.313496-62-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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*
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* This header file contains the interface of the interrupt remapping code to
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* the x86 interrupt management code.
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*/
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#ifndef __X86_IRQ_REMAPPING_H
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#define __X86_IRQ_REMAPPING_H
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#include <asm/irqdomain.h>
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#include <asm/hw_irq.h>
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#include <asm/io_apic.h>
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struct msi_msg;
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struct irq_alloc_info;
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enum irq_remap_cap {
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IRQ_POSTING_CAP = 0,
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};
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enum {
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IRQ_REMAP_XAPIC_MODE,
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IRQ_REMAP_X2APIC_MODE,
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};
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/*
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* This is mainly used to communicate information back-and-forth
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* between SVM and IOMMU for setting up and tearing down posted
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* interrupt
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*/
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struct amd_iommu_pi_data {
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u64 vapic_addr; /* Physical address of the vCPU's vAPIC. */
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u32 ga_tag;
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u32 vector; /* Guest vector of the interrupt */
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int cpu;
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bool ga_log_intr;
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bool is_guest_mode;
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void *ir_data;
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};
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struct intel_iommu_pi_data {
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u64 pi_desc_addr; /* Physical address of PI Descriptor */
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u32 vector; /* Guest vector of the interrupt */
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};
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#ifdef CONFIG_IRQ_REMAP
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extern raw_spinlock_t irq_2_ir_lock;
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extern bool irq_remapping_cap(enum irq_remap_cap cap);
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extern void set_irq_remapping_broken(void);
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extern int irq_remapping_prepare(void);
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extern int irq_remapping_enable(void);
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extern void irq_remapping_disable(void);
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extern int irq_remapping_reenable(int);
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extern int irq_remap_enable_fault_handling(void);
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extern void panic_if_irq_remap(const char *msg);
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/* Get parent irqdomain for interrupt remapping irqdomain */
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static inline struct irq_domain *arch_get_ir_parent_domain(void)
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{
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return x86_vector_domain;
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}
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extern bool enable_posted_msi;
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static inline bool posted_msi_supported(void)
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{
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return enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP);
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}
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#else /* CONFIG_IRQ_REMAP */
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static inline bool irq_remapping_cap(enum irq_remap_cap cap) { return 0; }
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static inline void set_irq_remapping_broken(void) { }
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static inline int irq_remapping_prepare(void) { return -ENODEV; }
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static inline int irq_remapping_enable(void) { return -ENODEV; }
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static inline void irq_remapping_disable(void) { }
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static inline int irq_remapping_reenable(int eim) { return -ENODEV; }
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static inline int irq_remap_enable_fault_handling(void) { return -ENODEV; }
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static inline void panic_if_irq_remap(const char *msg)
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{
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}
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#endif /* CONFIG_IRQ_REMAP */
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#endif /* __X86_IRQ_REMAPPING_H */
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