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b66fcee157
GCC may ignore the __no_sanitize_address function attribute when inlining, resulting in KASAN instrumentation in code tagged as 'noinstr'. Move the SEV NMI handling code, which is noinstr, into a separate source file so KASAN can be disabled on the whole file without losing coverage of other SEV core code, once the startup code is split off from it too. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: Dionna Amalie Glaze <dionnaglaze@google.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Kees Cook <keescook@chromium.org> Cc: Kevin Loughlin <kevinloughlin@google.com> Cc: Len Brown <len.brown@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20250418141253.2601348-10-ardb+git@google.com
108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AMD Memory Encryption Support
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*
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* Copyright (C) 2019 SUSE
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*
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* Author: Joerg Roedel <jroedel@suse.de>
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*/
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#define pr_fmt(fmt) "SEV: " fmt
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <asm/cpu_entry_area.h>
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#include <asm/msr.h>
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#include <asm/ptrace.h>
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#include <asm/sev.h>
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#include <asm/sev-internal.h>
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static __always_inline bool on_vc_stack(struct pt_regs *regs)
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{
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unsigned long sp = regs->sp;
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/* User-mode RSP is not trusted */
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if (user_mode(regs))
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return false;
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/* SYSCALL gap still has user-mode RSP */
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if (ip_within_syscall_gap(regs))
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return false;
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return ((sp >= __this_cpu_ist_bottom_va(VC)) && (sp < __this_cpu_ist_top_va(VC)));
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}
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/*
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* This function handles the case when an NMI is raised in the #VC
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* exception handler entry code, before the #VC handler has switched off
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* its IST stack. In this case, the IST entry for #VC must be adjusted,
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* so that any nested #VC exception will not overwrite the stack
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* contents of the interrupted #VC handler.
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*
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* The IST entry is adjusted unconditionally so that it can be also be
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* unconditionally adjusted back in __sev_es_ist_exit(). Otherwise a
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* nested sev_es_ist_exit() call may adjust back the IST entry too
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* early.
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*
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* The __sev_es_ist_enter() and __sev_es_ist_exit() functions always run
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* on the NMI IST stack, as they are only called from NMI handling code
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* right now.
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*/
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void noinstr __sev_es_ist_enter(struct pt_regs *regs)
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{
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unsigned long old_ist, new_ist;
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/* Read old IST entry */
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new_ist = old_ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]);
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/*
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* If NMI happened while on the #VC IST stack, set the new IST
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* value below regs->sp, so that the interrupted stack frame is
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* not overwritten by subsequent #VC exceptions.
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*/
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if (on_vc_stack(regs))
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new_ist = regs->sp;
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/*
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* Reserve additional 8 bytes and store old IST value so this
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* adjustment can be unrolled in __sev_es_ist_exit().
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*/
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new_ist -= sizeof(old_ist);
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*(unsigned long *)new_ist = old_ist;
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/* Set new IST entry */
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this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], new_ist);
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}
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void noinstr __sev_es_ist_exit(void)
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{
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unsigned long ist;
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/* Read IST entry */
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ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]);
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if (WARN_ON(ist == __this_cpu_ist_top_va(VC)))
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return;
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/* Read back old IST entry and write it to the TSS */
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this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], *(unsigned long *)ist);
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}
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void noinstr __sev_es_nmi_complete(void)
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{
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struct ghcb_state state;
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struct ghcb *ghcb;
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ghcb = __sev_get_ghcb(&state);
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vc_ghcb_invalidate(ghcb);
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ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_NMI_COMPLETE);
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ghcb_set_sw_exit_info_1(ghcb, 0);
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ghcb_set_sw_exit_info_2(ghcb, 0);
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sev_es_wr_ghcb_msr(__pa_nodebug(ghcb));
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VMGEXIT();
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__sev_put_ghcb(&state);
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}
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