Exact

Exact Union RegExp

Peilin Ye db7a3822b5 bpf, riscv64: Skip redundant zext instruction after load-acquire ... Currently, the verifier inserts a zext instruction right after every 8-, 16- or 32-bit load-acquire, which is already zero-extending. Skip such redundant zext instructions. While we are here, update that already-obsolete comment about "skip the next instruction" in build_body(). Also change emit_atomic_rmw()'s parameters to keep it consistent with emit_atomic_ld_st(). Note that checking 'insn[1]' relies on 'insn' not being the last instruction, which should have been guaranteed by the verifier; we already use 'insn[1]' elsewhere in the file for similar purposes. Additionally, we don't check if 'insn[1]' is actually a zext for our load-acquire's dst_reg, or some other registers - in other words, here we are relying on the verifier to always insert a redundant zext right after a 8/16/32-bit load-acquire, for its dst_reg. Acked-by: Björn Töpel <bjorn@kernel.org> Reviewed-by: Pu Lehui <pulehui@huawei.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> # QEMU/RVA23 Signed-off-by: Peilin Ye <yepeilin@google.com> Link: https://lore.kernel.org/r/10e90e0eab042f924d35ad0d1c1f7ca29f673152.1746588351.git.yepeilin@google.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>		2025-05-09 10:05:27 -07:00
..
bpf_jit.h	bpf, riscv64: Support load-acquire and store-release instructions	2025-05-09 10:05:27 -07:00
bpf_jit_comp32.c	riscv, bpf: Introduce shift add helper with Zba optimization	2024-06-03 16:45:23 +02:00
bpf_jit_comp64.c	bpf, riscv64: Skip redundant zext instruction after load-acquire	2025-05-09 10:05:27 -07:00
bpf_jit_core.c	bpf, riscv64: Skip redundant zext instruction after load-acquire	2025-05-09 10:05:27 -07:00
Makefile	riscv, bpf: Add RV32G eBPF JIT	2020-03-05 16:13:47 +01:00