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The current implementation is underperforming and in addition, it triggers misaligned access traps on platforms which do not handle misaligned accesses in hardware. Use the existing assembly routines to solve both problems at once. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20250602193918.868962-2-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
264 lines
6.2 KiB
ArmAsm
264 lines
6.2 KiB
ArmAsm
#include <linux/linkage.h>
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#include <linux/export.h>
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#include <asm/asm.h>
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#include <asm/asm-extable.h>
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#include <asm/csr.h>
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#include <asm/hwcap.h>
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#include <asm/alternative-macros.h>
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.macro fixup op reg addr lbl
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100:
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\op \reg, \addr
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_asm_extable 100b, \lbl
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.endm
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SYM_FUNC_START(__asm_copy_to_user)
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#ifdef CONFIG_RISCV_ISA_V
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ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_ZVE32X, CONFIG_RISCV_ISA_V)
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REG_L t0, riscv_v_usercopy_threshold
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bltu a2, t0, fallback_scalar_usercopy
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li a3, 1
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tail enter_vector_usercopy
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#endif
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SYM_FUNC_END(__asm_copy_to_user)
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EXPORT_SYMBOL(__asm_copy_to_user)
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SYM_FUNC_ALIAS(__asm_copy_from_user, __asm_copy_to_user)
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EXPORT_SYMBOL(__asm_copy_from_user)
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SYM_FUNC_START(fallback_scalar_usercopy)
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/* Enable access to user memory */
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li t6, SR_SUM
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csrs CSR_STATUS, t6
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mv t6, ra
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call fallback_scalar_usercopy_sum_enabled
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/* Disable access to user memory */
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mv ra, t6
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li t6, SR_SUM
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csrc CSR_STATUS, t6
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ret
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SYM_FUNC_END(fallback_scalar_usercopy)
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SYM_FUNC_START(__asm_copy_to_user_sum_enabled)
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#ifdef CONFIG_RISCV_ISA_V
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ALTERNATIVE("j fallback_scalar_usercopy_sum_enabled", "nop", 0, RISCV_ISA_EXT_ZVE32X, CONFIG_RISCV_ISA_V)
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REG_L t0, riscv_v_usercopy_threshold
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bltu a2, t0, fallback_scalar_usercopy_sum_enabled
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li a3, 0
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tail enter_vector_usercopy
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#endif
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SYM_FUNC_END(__asm_copy_to_user_sum_enabled)
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SYM_FUNC_ALIAS(__asm_copy_from_user_sum_enabled, __asm_copy_to_user_sum_enabled)
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EXPORT_SYMBOL(__asm_copy_from_user_sum_enabled)
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EXPORT_SYMBOL(__asm_copy_to_user_sum_enabled)
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SYM_FUNC_START(fallback_scalar_usercopy_sum_enabled)
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/*
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* Save the terminal address which will be used to compute the number
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* of bytes copied in case of a fixup exception.
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*/
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add t5, a0, a2
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/*
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* Register allocation for code below:
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* a0 - start of uncopied dst
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* a1 - start of uncopied src
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* a2 - size
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* t0 - end of uncopied dst
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*/
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add t0, a0, a2
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/*
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* Use byte copy only if too small.
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* SZREG holds 4 for RV32 and 8 for RV64
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*/
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li a3, 9*SZREG-1 /* size must >= (word_copy stride + SZREG-1) */
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bltu a2, a3, .Lbyte_copy_tail
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/*
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* Copy first bytes until dst is aligned to word boundary.
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* a0 - start of dst
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* t1 - start of aligned dst
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*/
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addi t1, a0, SZREG-1
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andi t1, t1, ~(SZREG-1)
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/* dst is already aligned, skip */
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beq a0, t1, .Lskip_align_dst
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1:
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/* a5 - one byte for copying data */
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fixup lb a5, 0(a1), 10f
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addi a1, a1, 1 /* src */
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fixup sb a5, 0(a0), 10f
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addi a0, a0, 1 /* dst */
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bltu a0, t1, 1b /* t1 - start of aligned dst */
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.Lskip_align_dst:
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/*
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* Now dst is aligned.
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* Use shift-copy if src is misaligned.
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* Use word-copy if both src and dst are aligned because
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* can not use shift-copy which do not require shifting
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*/
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/* a1 - start of src */
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andi a3, a1, SZREG-1
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bnez a3, .Lshift_copy
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.Lword_copy:
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/*
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* Both src and dst are aligned, unrolled word copy
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*
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* a0 - start of aligned dst
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* a1 - start of aligned src
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* t0 - end of aligned dst
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*/
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addi t0, t0, -(8*SZREG) /* not to over run */
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2:
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fixup REG_L a4, 0(a1), 10f
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fixup REG_L a5, SZREG(a1), 10f
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fixup REG_L a6, 2*SZREG(a1), 10f
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fixup REG_L a7, 3*SZREG(a1), 10f
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fixup REG_L t1, 4*SZREG(a1), 10f
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fixup REG_L t2, 5*SZREG(a1), 10f
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fixup REG_L t3, 6*SZREG(a1), 10f
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fixup REG_L t4, 7*SZREG(a1), 10f
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fixup REG_S a4, 0(a0), 10f
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fixup REG_S a5, SZREG(a0), 10f
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fixup REG_S a6, 2*SZREG(a0), 10f
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fixup REG_S a7, 3*SZREG(a0), 10f
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fixup REG_S t1, 4*SZREG(a0), 10f
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fixup REG_S t2, 5*SZREG(a0), 10f
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fixup REG_S t3, 6*SZREG(a0), 10f
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fixup REG_S t4, 7*SZREG(a0), 10f
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addi a0, a0, 8*SZREG
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addi a1, a1, 8*SZREG
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bleu a0, t0, 2b
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addi t0, t0, 8*SZREG /* revert to original value */
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j .Lbyte_copy_tail
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.Lshift_copy:
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/*
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* Word copy with shifting.
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* For misaligned copy we still perform aligned word copy, but
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* we need to use the value fetched from the previous iteration and
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* do some shifts.
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* This is safe because reading is less than a word size.
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*
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* a0 - start of aligned dst
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* a1 - start of src
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* a3 - a1 & mask:(SZREG-1)
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* t0 - end of uncopied dst
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* t1 - end of aligned dst
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*/
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/* calculating aligned word boundary for dst */
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andi t1, t0, ~(SZREG-1)
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/* Converting unaligned src to aligned src */
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andi a1, a1, ~(SZREG-1)
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/*
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* Calculate shifts
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* t3 - prev shift
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* t4 - current shift
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*/
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slli t3, a3, 3 /* converting bytes in a3 to bits */
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li a5, SZREG*8
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sub t4, a5, t3
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/* Load the first word to combine with second word */
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fixup REG_L a5, 0(a1), 10f
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3:
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/* Main shifting copy
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*
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* a0 - start of aligned dst
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* a1 - start of aligned src
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* t1 - end of aligned dst
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*/
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/* At least one iteration will be executed */
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srl a4, a5, t3
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fixup REG_L a5, SZREG(a1), 10f
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addi a1, a1, SZREG
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sll a2, a5, t4
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or a2, a2, a4
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fixup REG_S a2, 0(a0), 10f
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addi a0, a0, SZREG
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bltu a0, t1, 3b
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/* Revert src to original unaligned value */
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add a1, a1, a3
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.Lbyte_copy_tail:
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/*
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* Byte copy anything left.
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*
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* a0 - start of remaining dst
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* a1 - start of remaining src
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* t0 - end of remaining dst
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*/
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bgeu a0, t0, .Lout_copy_user /* check if end of copy */
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4:
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fixup lb a5, 0(a1), 10f
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addi a1, a1, 1 /* src */
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fixup sb a5, 0(a0), 10f
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addi a0, a0, 1 /* dst */
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bltu a0, t0, 4b /* t0 - end of dst */
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.Lout_copy_user:
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li a0, 0
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ret
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10:
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sub a0, t5, a0
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ret
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SYM_FUNC_END(fallback_scalar_usercopy_sum_enabled)
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SYM_FUNC_START(__clear_user)
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/* Enable access to user memory */
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li t6, SR_SUM
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csrs CSR_STATUS, t6
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add a3, a0, a1
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addi t0, a0, SZREG-1
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andi t1, a3, ~(SZREG-1)
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andi t0, t0, ~(SZREG-1)
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/*
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* a3: terminal address of target region
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* t0: lowest doubleword-aligned address in target region
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* t1: highest doubleword-aligned address in target region
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*/
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bgeu t0, t1, 2f
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bltu a0, t0, 4f
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1:
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fixup REG_S, zero, (a0), 11f
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addi a0, a0, SZREG
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bltu a0, t1, 1b
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2:
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bltu a0, a3, 5f
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3:
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/* Disable access to user memory */
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csrc CSR_STATUS, t6
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li a0, 0
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ret
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4: /* Edge case: unalignment */
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fixup sb, zero, (a0), 11f
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addi a0, a0, 1
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bltu a0, t0, 4b
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j 1b
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5: /* Edge case: remainder */
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fixup sb, zero, (a0), 11f
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addi a0, a0, 1
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bltu a0, a3, 5b
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j 3b
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/* Exception fixup code */
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11:
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/* Disable access to user memory */
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csrc CSR_STATUS, t6
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sub a0, a3, a0
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ret
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SYM_FUNC_END(__clear_user)
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EXPORT_SYMBOL(__clear_user)
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