mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00

"riscv: signal: Report signal frame size to userspace via auxv" (e92f469
) has added new constant AT_MINSIGSTKSZ but failed to increment the size of auxv, keeping AT_VECTOR_SIZE_ARCH at 9. This fix correctly increments AT_VECTOR_SIZE_ARCH to 10, following the approach in the commit94b07c1
("arm64: signal: Report signal frame size to userspace via auxv"). Link: https://lore.kernel.org/r/73883406.20231215232720@torrio.net Link: https://lore.kernel.org/all/20240102133617.3649-1-victor@torrio.net/ Reported-by: Ivan Komarov <ivan.komarov@dfyz.info> Closes: https://lore.kernel.org/linux-riscv/CY3Z02NYV1C4.11BLB9PLVW9G1@fedora/ Fixes:e92f469b07
("riscv: signal: Report signal frame size to userspace via auxv") Signed-off-by: Victor Isaev <isv@google.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
40 lines
1.2 KiB
C
40 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
|
|
/*
|
|
* Copyright (C) 2012 ARM Ltd.
|
|
* Copyright (C) 2015 Regents of the University of California
|
|
*/
|
|
|
|
#ifndef _UAPI_ASM_RISCV_AUXVEC_H
|
|
#define _UAPI_ASM_RISCV_AUXVEC_H
|
|
|
|
/* vDSO location */
|
|
#define AT_SYSINFO_EHDR 33
|
|
|
|
/*
|
|
* The set of entries below represent more extensive information
|
|
* about the caches, in the form of two entry per cache type,
|
|
* one entry containing the cache size in bytes, and the other
|
|
* containing the cache line size in bytes in the bottom 16 bits
|
|
* and the cache associativity in the next 16 bits.
|
|
*
|
|
* The associativity is such that if N is the 16-bit value, the
|
|
* cache is N way set associative. A value if 0xffff means fully
|
|
* associative, a value of 1 means directly mapped.
|
|
*
|
|
* For all these fields, a value of 0 means that the information
|
|
* is not known.
|
|
*/
|
|
#define AT_L1I_CACHESIZE 40
|
|
#define AT_L1I_CACHEGEOMETRY 41
|
|
#define AT_L1D_CACHESIZE 42
|
|
#define AT_L1D_CACHEGEOMETRY 43
|
|
#define AT_L2_CACHESIZE 44
|
|
#define AT_L2_CACHEGEOMETRY 45
|
|
#define AT_L3_CACHESIZE 46
|
|
#define AT_L3_CACHEGEOMETRY 47
|
|
|
|
/* entries in ARCH_DLINFO */
|
|
#define AT_VECTOR_SIZE_ARCH 10
|
|
#define AT_MINSIGSTKSZ 51
|
|
|
|
#endif /* _UAPI_ASM_RISCV_AUXVEC_H */
|