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RISC-V APLIC specification defines "hart index" in [1]. Similar definitions can be found for ACLINT in [2] Quote from the APLIC specification: Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, it says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indices specified in an optional property "riscv,hart-indexes" which is specified as an array of u32 elements, one per interrupt target, listing hart indexes in the same order as in "interrupts-extended". If this property is not specified, fall back to use logical hart indices within the domain. Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250612143911.3224046-2-vladimir.kondratiev@mobileye.com Link: https://github.com/riscv/riscv-aia [1] Link: https://github.com/riscvarchive/riscv-aclint [2]
81 lines
2.2 KiB
C
81 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_IRQ_H
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#define _ASM_RISCV_IRQ_H
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#include <linux/interrupt.h>
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#include <linux/linkage.h>
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#include <asm-generic/irq.h>
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#define INVALID_CONTEXT UINT_MAX
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#ifdef CONFIG_SMP
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void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu);
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#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
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#endif
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void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));
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struct fwnode_handle *riscv_get_intc_hwnode(void);
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int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index,
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u32 *hart_index);
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#ifdef CONFIG_ACPI
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enum riscv_irqchip_type {
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ACPI_RISCV_IRQCHIP_INTC = 0x00,
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ACPI_RISCV_IRQCHIP_IMSIC = 0x01,
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ACPI_RISCV_IRQCHIP_PLIC = 0x02,
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ACPI_RISCV_IRQCHIP_APLIC = 0x03,
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};
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int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
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u32 *id, u32 *nr_irqs, u32 *nr_idcs);
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struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi);
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unsigned long acpi_rintc_index_to_hartid(u32 index);
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unsigned long acpi_rintc_ext_parent_to_hartid(unsigned int plic_id, unsigned int ctxt_idx);
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unsigned int acpi_rintc_get_plic_nr_contexts(unsigned int plic_id);
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unsigned int acpi_rintc_get_plic_context(unsigned int plic_id, unsigned int ctxt_idx);
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int __init acpi_rintc_get_imsic_mmio_info(u32 index, struct resource *res);
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#else
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static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
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u32 *id, u32 *nr_irqs, u32 *nr_idcs)
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{
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return 0;
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}
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static inline unsigned long acpi_rintc_index_to_hartid(u32 index)
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{
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return INVALID_HARTID;
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}
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static inline unsigned long acpi_rintc_ext_parent_to_hartid(unsigned int plic_id,
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unsigned int ctxt_idx)
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{
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return INVALID_HARTID;
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}
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static inline unsigned int acpi_rintc_get_plic_nr_contexts(unsigned int plic_id)
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{
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return INVALID_CONTEXT;
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}
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static inline unsigned int acpi_rintc_get_plic_context(unsigned int plic_id, unsigned int ctxt_idx)
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{
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return INVALID_CONTEXT;
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}
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static inline int __init acpi_rintc_get_imsic_mmio_info(u32 index, struct resource *res)
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{
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return 0;
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}
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#endif /* CONFIG_ACPI */
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#endif /* _ASM_RISCV_IRQ_H */
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