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4bf9706923
Follow the patterns of the other architectures that use GENERIC_CPU_VULNERABILITIES for riscv to introduce the ghostwrite vulnerability and mitigation. The mitigation is to disable all vector which is accomplished by clearing the bit from the cpufeature field. Ghostwrite only affects thead c9xx CPUs that impelment xtheadvector, so the vulerability will only be mitigated on these CPUs. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-14-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
128 lines
3.7 KiB
C
128 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Sifive.
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*/
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#ifndef ASM_ERRATA_LIST_H
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#define ASM_ERRATA_LIST_H
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#include <asm/alternative.h>
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#include <asm/csr.h>
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#include <asm/insn-def.h>
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#include <asm/hwcap.h>
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#include <asm/vendorid_list.h>
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#ifdef CONFIG_ERRATA_ANDES
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#define ERRATA_ANDES_NO_IOCP 0
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#define ERRATA_ANDES_NUMBER 1
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#endif
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#ifdef CONFIG_ERRATA_SIFIVE
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#define ERRATA_SIFIVE_CIP_453 0
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#define ERRATA_SIFIVE_CIP_1200 1
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#define ERRATA_SIFIVE_NUMBER 2
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#endif
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#ifdef CONFIG_ERRATA_THEAD
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#define ERRATA_THEAD_MAE 0
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#define ERRATA_THEAD_PMU 1
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#define ERRATA_THEAD_GHOSTWRITE 2
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#define ERRATA_THEAD_NUMBER 3
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#endif
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#ifdef __ASSEMBLY__
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#define ALT_INSN_FAULT(x) \
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ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \
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__stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \
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SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
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CONFIG_ERRATA_SIFIVE_CIP_453)
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#define ALT_PAGE_FAULT(x) \
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ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \
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__stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \
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SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
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CONFIG_ERRATA_SIFIVE_CIP_453)
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#else /* !__ASSEMBLY__ */
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#define ALT_SFENCE_VMA_ASID(asid) \
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asm(ALTERNATIVE("sfence.vma x0, %0", "sfence.vma", SIFIVE_VENDOR_ID, \
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ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
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: : "r" (asid) : "memory")
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#define ALT_SFENCE_VMA_ADDR(addr) \
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asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
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ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
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: : "r" (addr) : "memory")
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#define ALT_SFENCE_VMA_ADDR_ASID(addr, asid) \
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asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIVE_VENDOR_ID, \
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ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
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: : "r" (addr), "r" (asid) : "memory")
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/*
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* _val is marked as "will be overwritten", so need to set it to 0
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* in the default case.
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*/
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#define ALT_SVPBMT_SHIFT 61
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#define ALT_THEAD_MAE_SHIFT 59
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#define ALT_SVPBMT(_val, prot) \
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asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
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"li %0, %1\t\nslli %0,%0,%3", 0, \
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RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \
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"li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \
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ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \
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: "=r"(_val) \
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: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
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"I"(prot##_THEAD >> ALT_THEAD_MAE_SHIFT), \
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"I"(ALT_SVPBMT_SHIFT), \
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"I"(ALT_THEAD_MAE_SHIFT))
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#ifdef CONFIG_ERRATA_THEAD_MAE
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/*
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* IO/NOCACHE memory types are handled together with svpbmt,
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* so on T-Head chips, check if no other memory type is set,
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* and set the non-0 PMA type if applicable.
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*/
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#define ALT_THEAD_PMA(_val) \
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asm volatile(ALTERNATIVE( \
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__nops(7), \
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"li t3, %1\n\t" \
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"slli t3, t3, %3\n\t" \
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"and t3, %0, t3\n\t" \
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"bne t3, zero, 2f\n\t" \
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"li t3, %2\n\t" \
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"slli t3, t3, %3\n\t" \
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"or %0, %0, t3\n\t" \
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"2:", THEAD_VENDOR_ID, \
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ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \
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: "+r"(_val) \
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: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAE_SHIFT), \
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"I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAE_SHIFT), \
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"I"(ALT_THEAD_MAE_SHIFT) \
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: "t3")
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#else
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#define ALT_THEAD_PMA(_val)
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#endif
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#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
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asm volatile(ALTERNATIVE( \
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__nops(5), \
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"mv a0, %1\n\t" \
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"j 2f\n\t" \
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"3:\n\t" \
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CBO_##_op(a0) \
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"add a0, a0, %0\n\t" \
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"2:\n\t" \
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"bltu a0, %2, 3b\n\t", \
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0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM) \
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: : "r"(_cachesize), \
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"r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
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"r"((unsigned long)(_start) + (_size)) \
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: "a0")
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#define THEAD_C9XX_RV_IRQ_PMU 17
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#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5
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#endif /* __ASSEMBLY__ */
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#endif
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