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2670a39b1e
riscv patches for 6.16-rc1, part 2 * Performance improvements - Add support for vdso getrandom - Implement raid6 calculations using vectors - Introduce svinval tlb invalidation * Cleanup - A bunch of deduplication of the macros we use for manipulating instructions * Misc - Introduce a kunit test for kprobes - Add support for mseal as riscv fits the requirements (thanks to Lorenzo for making sure of that :)) [Palmer: There was a rebase between part 1 and part 2, so I've had to do some more git surgery here... at least two rounds of surgery...] * alex-pr-2: (866 commits) RISC-V: vDSO: Wire up getrandom() vDSO implementation riscv: enable mseal sysmap for RV64 raid6: Add RISC-V SIMD syndrome and recovery calculations riscv: mm: Add support for Svinval extension riscv: Add kprobes KUnit test riscv: kprobes: Remove duplication of RV_EXTRACT_ITYPE_IMM riscv: kprobes: Remove duplication of RV_EXTRACT_UTYPE_IMM riscv: kprobes: Remove duplication of RV_EXTRACT_RD_REG riscv: kprobes: Remove duplication of RVC_EXTRACT_BTYPE_IMM riscv: kprobes: Remove duplication of RVC_EXTRACT_C2_RS1_REG riscv: kproves: Remove duplication of RVC_EXTRACT_JTYPE_IMM riscv: kprobes: Remove duplication of RV_EXTRACT_BTYPE_IMM riscv: kprobes: Remove duplication of RV_EXTRACT_RS1_REG riscv: kprobes: Remove duplication of RV_EXTRACT_JTYPE_IMM riscv: kprobes: Move branch_funct3 to insn.h riscv: kprobes: Move branch_rs2_idx to insn.h Linux 6.15-rc6 Input: xpad - fix xpad_device sorting Input: xpad - add support for several more controllers Input: xpad - fix Share button on Xbox One controllers ...
107 lines
2.7 KiB
C
107 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CACHEFLUSH_H
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#define _ASM_RISCV_CACHEFLUSH_H
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#include <linux/mm.h>
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static inline void local_flush_icache_all(void)
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{
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asm volatile ("fence.i" ::: "memory");
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}
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static inline void local_flush_icache_range(unsigned long start,
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unsigned long end)
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{
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local_flush_icache_all();
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}
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#define PG_dcache_clean PG_arch_1
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static inline void flush_dcache_folio(struct folio *folio)
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{
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if (test_bit(PG_dcache_clean, &folio->flags))
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clear_bit(PG_dcache_clean, &folio->flags);
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}
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#define flush_dcache_folio flush_dcache_folio
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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static inline void flush_dcache_page(struct page *page)
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{
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flush_dcache_folio(page_folio(page));
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}
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#define flush_icache_user_page(vma, pg, addr, len) \
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do { \
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if (vma->vm_flags & VM_EXEC) \
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flush_icache_mm(vma->vm_mm, 0); \
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} while (0)
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#ifdef CONFIG_64BIT
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extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1];
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extern char _end[];
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#define flush_cache_vmap flush_cache_vmap
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static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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{
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if (is_vmalloc_or_module_addr((void *)start)) {
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int i;
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/*
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* We don't care if concurrently a cpu resets this value since
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* the only place this can happen is in handle_exception() where
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* an sfence.vma is emitted.
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*/
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for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i)
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new_vmalloc[i] = -1ULL;
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}
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}
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#define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end)
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#endif
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#ifndef CONFIG_SMP
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#define flush_icache_all() local_flush_icache_all()
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#define flush_icache_mm(mm, local) flush_icache_all()
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#else /* CONFIG_SMP */
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void flush_icache_all(void);
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void flush_icache_mm(struct mm_struct *mm, bool local);
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#endif /* CONFIG_SMP */
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/*
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* RISC-V doesn't have an instruction to flush parts of the instruction cache,
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* so instead we just flush the whole thing.
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*/
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#define flush_icache_range flush_icache_range
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static inline void flush_icache_range(unsigned long start, unsigned long end)
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{
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flush_icache_all();
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}
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extern unsigned int riscv_cbom_block_size;
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extern unsigned int riscv_cboz_block_size;
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extern unsigned int riscv_cbop_block_size;
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void riscv_init_cbo_blocksizes(void);
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#ifdef CONFIG_RISCV_DMA_NONCOHERENT
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void riscv_noncoherent_supported(void);
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void __init riscv_set_dma_cache_alignment(void);
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#else
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static inline void riscv_noncoherent_supported(void) {}
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static inline void riscv_set_dma_cache_alignment(void) {}
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#endif
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/*
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* Bits in sys_riscv_flush_icache()'s flags argument.
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*/
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#define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
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#define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL)
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#include <asm-generic/cacheflush.h>
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#endif /* _ASM_RISCV_CACHEFLUSH_H */
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