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a2e7f6c487
Add usb_cdns3 and usb0_pins configuration to support super speed USB device on the FML13V01 board. Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io> Tested-by: Maud Spierings <maud_spierings@hotmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
70 lines
1.3 KiB
Text
70 lines
1.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2024 DeepComputing (HK) Limited
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*/
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/dts-v1/;
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#include "jh7110-common.dtsi"
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/ {
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model = "DeepComputing FML13V01";
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compatible = "deepcomputing,fml13v01", "starfive,jh7110";
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};
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&pcie1 {
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perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
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phys = <&pciephy1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_pins>;
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status = "okay";
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};
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&sysgpio {
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pcie1_pins: pcie1-0 {
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clkreq-pins {
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pinmux = <GPIOMUX(29, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_NONE)>;
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bias-pull-down;
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drive-strength = <2>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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wake-pins {
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pinmux = <GPIOMUX(28, GPOUT_HIGH,
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GPOEN_DISABLE,
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GPI_NONE)>;
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bias-pull-up;
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drive-strength = <2>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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usb0_pins: usb0-0 {
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vbus-pins {
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pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
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GPOEN_ENABLE,
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GPI_NONE)>;
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bias-disable;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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};
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&usb0 {
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dr_mode = "host";
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pinctrl-names = "default";
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pinctrl-0 = <&usb0_pins>;
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status = "okay";
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};
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&usb_cdns3 {
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phys = <&usbphy0>, <&pciephy0>;
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phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
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};
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