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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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3309df45e6
Add PCIe device node for SG2044 and configuration for Sophgo SRD3-10. Link: https://lore.kernel.org/r/20250618015851.272188-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
585 lines
17 KiB
Text
585 lines
17 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
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*/
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#include <dt-bindings/clock/sophgo,sg2044-pll.h>
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#include <dt-bindings/clock/sophgo,sg2044-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-sg2044.h>
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#include "sg2044-cpus.dtsi"
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#include "sg2044-reset.h"
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/ {
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compatible = "sophgo,sg2044";
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000010 0x00000000>;
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};
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osc: oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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pcie0: pcie@6c00000000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x00000000 0x0 0x00001000>,
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<0x6c 0x00300000 0x0 0x00004000>,
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<0x48 0x00000000 0x0 0x00001000>,
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<0x6c 0x000c0000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>,
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<0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>,
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<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
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<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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pcie1: pcie@6c00400000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x00400000 0x0 0x00001000>,
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<0x6c 0x00700000 0x0 0x00004000>,
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<0x40 0x00000000 0x0 0x00001000>,
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<0x6c 0x00780000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>,
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<0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>,
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<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
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<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc1: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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pcie2: pcie@6c04000000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x04000000 0x0 0x00001000>,
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<0x6c 0x04300000 0x0 0x00004000>,
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<0x58 0x00000000 0x0 0x00001000>,
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<0x6c 0x040c0000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc2 0>,
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<0 0 0 2 &pcie_intc2 1>,
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<0 0 0 3 &pcie_intc2 2>,
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<0 0 0 4 &pcie_intc2 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>,
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<0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>,
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<0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
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<0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc2: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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pcie3: pcie@6c04400000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x04400000 0x0 0x00001000>,
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<0x6c 0x04700000 0x0 0x00004000>,
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<0x50 0x00000000 0x0 0x00001000>,
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<0x6c 0x04780000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc3 0>,
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<0 0 0 2 &pcie_intc3 1>,
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<0 0 0 3 &pcie_intc3 2>,
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<0 0 0 4 &pcie_intc3 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>,
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<0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>,
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<0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
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<0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc3: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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pcie4: pcie@6c08400000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x08400000 0x0 0x00001000>,
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<0x6c 0x08700000 0x0 0x00004000>,
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<0x60 0x00000000 0x0 0x00001000>,
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<0x6c 0x08780000 0x0 0x00001000>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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clocks = <&clk CLK_GATE_PCIE_1G>;
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clock-names = "core";
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device_type = "pci";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc4 0>,
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<0 0 0 2 &pcie_intc4 1>,
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<0 0 0 3 &pcie_intc4 2>,
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<0 0 0 4 &pcie_intc4 3>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x40000000 0x0 0x40000000 0x0 0x04000000>,
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<0x02000000 0x0 0x44000000 0x0 0x44000000 0x0 0x04000000>,
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<0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
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<0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
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status = "disabled";
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pcie_intc4: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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};
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};
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msi: msi-controller@6d50000000 {
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compatible = "sophgo,sg2044-msi";
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reg = <0x6d 0x50000000 0x0 0x800>,
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<0x0 0x7ee00000 0x0 0x40>;
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reg-names = "clr", "doorbell";
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#msi-cells = <0>;
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msi-controller;
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msi-ranges = <&intc 352 IRQ_TYPE_LEVEL_HIGH 512>;
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status = "disabled";
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};
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spifmc0: spi@7001000000 {
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compatible = "sophgo,sg2044-spifmc-nor";
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reg = <0x70 0x01000000 0x0 0x4000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_GATE_AHB_SPIFMC>;
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interrupt-parent = <&intc>;
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interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPIFMC0>;
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status = "disabled";
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};
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spifmc1: spi@7005000000 {
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compatible = "sophgo,sg2044-spifmc-nor";
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reg = <0x70 0x05000000 0x0 0x4000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_GATE_AHB_SPIFMC>;
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interrupt-parent = <&intc>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPIFMC1>;
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status = "disabled";
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};
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dmac0: dma-controller@7020000000 {
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compatible = "snps,axi-dma-1.01a";
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reg = <0x70 0x20000000 0x0 0x10000>;
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#dma-cells = <1>;
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clock-names = "core-clk", "cfgr-clk";
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clocks = <&clk CLK_GATE_SYSDMA_AXI>,
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<&clk CLK_GATE_SYSDMA_AXI>;
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dma-noncoherent;
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interrupt-parent = <&intc>;
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interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
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dma-channels = <8>;
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snps,priority = <0 1 2 3 4 5 6 7>;
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snps,block-size = <4096 4096 4096 4096
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4096 4096 4096 4096>;
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snps,dma-masters = <2>;
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snps,data-width = <2>;
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snps,axi-max-burst-len = <4>;
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status = "disabled";
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};
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uart0: serial@7030000000 {
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compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
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reg = <0x70 0x30000000 0x0 0x1000>;
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clock-frequency = <500000000>;
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clocks = <&clk CLK_GATE_UART_500M>,
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<&clk CLK_GATE_APB_UART>;
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clock-names = "baudclk", "apb_pclk";
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interrupt-parent = <&intc>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART0>;
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status = "disabled";
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};
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uart1: serial@7030001000 {
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compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
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reg = <0x70 0x30001000 0x0 0x1000>;
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clock-frequency = <500000000>;
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clocks = <&clk CLK_GATE_UART_500M>,
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<&clk CLK_GATE_APB_UART>;
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clock-names = "baudclk", "apb_pclk";
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interrupt-parent = <&intc>;
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART1>;
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status = "disabled";
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};
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uart2: serial@7030002000 {
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compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
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reg = <0x70 0x30002000 0x0 0x1000>;
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clock-frequency = <500000000>;
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clocks = <&clk CLK_GATE_UART_500M>,
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<&clk CLK_GATE_APB_UART>;
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clock-names = "baudclk", "apb_pclk";
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interrupt-parent = <&intc>;
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interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART2>;
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status = "disabled";
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};
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uart3: serial@7030003000 {
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compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
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reg = <0x70 0x30003000 0x0 0x1000>;
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clock-frequency = <500000000>;
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clocks = <&clk CLK_GATE_UART_500M>,
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<&clk CLK_GATE_APB_UART>;
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clock-names = "baudclk", "apb_pclk";
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interrupt-parent = <&intc>;
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interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART3>;
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status = "disabled";
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};
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gmac0: ethernet@7030006000 {
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compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a";
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reg = <0x70 0x30006000 0x0 0x4000>;
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clocks = <&clk CLK_GATE_AXI_ETH0>,
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<&clk CLK_GATE_PTP_REF_I_ETH0>,
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<&clk CLK_GATE_TX_ETH0>;
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clock-names = "stmmaceth", "ptp_ref", "tx";
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dma-noncoherent;
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interrupt-parent = <&intc>;
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interrupts = <296 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&rst RST_ETH0>;
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reset-names = "stmmaceth";
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snps,multicast-filter-bins = <0>;
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snps,perfect-filter-entries = <1>;
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snps,aal;
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snps,tso;
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snps,txpbl = <32>;
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snps,rxpbl = <32>;
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snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
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snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
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snps,axi-config = <&gmac0_stmmac_axi_setup>;
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status = "disabled";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gmac0_mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <8>;
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snps,rx-sched-wsp;
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queue0 {};
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queue1 {};
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queue2 {};
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queue3 {};
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queue4 {};
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queue5 {};
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queue6 {};
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queue7 {};
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};
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gmac0_mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <8>;
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queue0 {};
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queue1 {};
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queue2 {};
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queue3 {};
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queue4 {};
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queue5 {};
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queue6 {};
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queue7 {};
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};
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gmac0_stmmac_axi_setup: stmmac-axi-config {
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snps,blen = <16 8 4 0 0 0 0>;
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snps,wr_osr_lmt = <1>;
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snps,rd_osr_lmt = <2>;
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};
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};
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emmc: mmc@703000a000 {
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compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
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reg = <0x70 0x3000a000 0x0 0x1000>;
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clocks = <&clk CLK_GATE_EMMC>,
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<&clk CLK_GATE_AXI_EMMC>,
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<&clk CLK_GATE_EMMC_100K>;
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clock-names = "core", "bus", "timer";
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interrupt-parent = <&intc>;
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interrupts = <298 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sd: mmc@703000b000 {
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compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
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reg = <0x70 0x3000b000 0x0 0x1000>;
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clocks = <&clk CLK_GATE_SD>,
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<&clk CLK_GATE_AXI_SD>,
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<&clk CLK_GATE_SD_100K>;
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clock-names = "core", "bus", "timer";
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interrupt-parent = <&intc>;
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interrupts = <300 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c0: i2c@7040005000 {
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compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
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reg = <0x70 0x40005000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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clocks = <&clk CLK_GATE_APB_I2C>;
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clock-names = "ref";
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interrupt-parent = <&intc>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@7040006000 {
|
|
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
|
|
reg = <0x70 0x40006000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-frequency = <100000>;
|
|
clocks = <&clk CLK_GATE_APB_I2C>;
|
|
clock-names = "ref";
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&rst RST_I2C1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@7040007000 {
|
|
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
|
|
reg = <0x70 0x40007000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-frequency = <100000>;
|
|
clocks = <&clk CLK_GATE_APB_I2C>;
|
|
clock-names = "ref";
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&rst RST_I2C2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@7040008000 {
|
|
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
|
|
reg = <0x70 0x40008000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-frequency = <100000>;
|
|
clocks = <&clk CLK_GATE_APB_I2C>;
|
|
clock-names = "ref";
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&rst RST_I2C3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio0: gpio@7040009000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0x70 0x40009000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clk CLK_GATE_APB_GPIO>,
|
|
<&clk CLK_GATE_GPIO_DB>;
|
|
clock-names = "bus", "db";
|
|
resets = <&rst RST_GPIO0>;
|
|
|
|
porta: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
reg = <0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
gpio1: gpio@704000a000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0x70 0x4000a000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clk CLK_GATE_APB_GPIO>,
|
|
<&clk CLK_GATE_GPIO_DB>;
|
|
clock-names = "bus", "db";
|
|
resets = <&rst RST_GPIO1>;
|
|
|
|
portb: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
reg = <0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
gpio2: gpio@704000b000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0x70 0x4000b000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clk CLK_GATE_APB_GPIO>,
|
|
<&clk CLK_GATE_GPIO_DB>;
|
|
clock-names = "bus", "db";
|
|
resets = <&rst RST_GPIO2>;
|
|
|
|
portc: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
reg = <0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
pwm: pwm@704000c000 {
|
|
compatible = "sophgo,sg2044-pwm";
|
|
reg = <0x70 0x4000c000 0x0 0x1000>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&clk CLK_GATE_APB_PWM>;
|
|
clock-names = "apb";
|
|
resets = <&rst RST_PWM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
syscon: syscon@7050000000 {
|
|
compatible = "sophgo,sg2044-top-syscon", "syscon";
|
|
reg = <0x70 0x50000000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&osc>;
|
|
};
|
|
|
|
pinctrl: pinctrl@7050001000 {
|
|
compatible = "sophgo,sg2044-pinctrl";
|
|
reg = <0x70 0x50001000 0x0 0x1000>;
|
|
};
|
|
|
|
clk: clock-controller@7050002000 {
|
|
compatible = "sophgo,sg2044-clk";
|
|
reg = <0x70 0x50002000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
|
|
<&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
|
|
<&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
|
|
<&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
|
|
<&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
|
|
<&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
|
|
<&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
|
|
<&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
|
|
<&syscon CLK_MPLL5>;
|
|
clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
|
|
"dpll1", "dpll2", "dpll3", "dpll4",
|
|
"dpll5", "dpll6", "dpll7", "mpll0",
|
|
"mpll1", "mpll2", "mpll3", "mpll4",
|
|
"mpll5";
|
|
};
|
|
|
|
rst: reset-controller@7050003000 {
|
|
compatible = "sophgo,sg2044-reset",
|
|
"sophgo,sg2042-reset";
|
|
reg = <0x70 0x50003000 0x0 0x1000>;
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
};
|