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ae5bac370e
Sophgo SG2044 SRD3-10 board bases on Sophgo SG2044 SoC. This board includes 5 uart ports, 5 pcie x8 slots, 1 1G Ethernet port, 1 microSD slot. Add initial device tree of this board with uart support. Link: https://lore.kernel.org/r/20250413223507.46480-11-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
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*/
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#ifndef _SG2044_RESET_H
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#define _SG2044_RESET_H
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#define RST_AP_SYS 0
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#define RST_AP_SYS_CORE0 1
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#define RST_AP_SYS_CORE1 2
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#define RST_AP_SYS_CORE2 3
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#define RST_AP_SYS_CORE3 4
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#define RST_AP_PIC 5
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#define RST_AP_TDT 6
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#define RST_RP_PIC_TDT 7
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#define RST_HSDMA 8
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#define RST_SYSDMA 9
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#define RST_EFUSE0 10
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#define RST_EFUSE1 11
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#define RST_RTC 12
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#define RST_TIMER 13
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#define RST_WDT 14
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#define RST_AHB_ROM0 15
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#define RST_AHB_ROM1 16
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#define RST_I2C0 17
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#define RST_I2C1 18
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#define RST_I2C2 19
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#define RST_I2C3 20
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#define RST_GPIO0 21
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#define RST_GPIO1 22
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#define RST_GPIO2 23
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#define RST_PWM 24
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#define RST_AXI_SRAM0 25
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#define RST_AXI_SRAM1 26
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#define RST_SPIFMC0 27
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#define RST_SPIFMC1 28
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#define RST_MAILBOX 29
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#define RST_ETH0 30
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#define RST_EMMC 31
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#define RST_SD 32
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#define RST_UART0 33
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#define RST_UART1 34
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#define RST_UART2 35
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#define RST_UART3 36
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#define RST_SPI0 37
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#define RST_SPI1 38
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#define RST_MTLI 39
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#define RST_DBG_I2C 40
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#define RST_C2C0 41
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#define RST_C2C1 42
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#define RST_C2C2 43
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#define RST_C2C3 44
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#define RST_CXP 45
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#define RST_DDR0 46
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#define RST_DDR1 47
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#define RST_DDR2 48
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#define RST_DDR3 49
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#define RST_DDR4 50
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#define RST_DDR5 51
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#define RST_DDR6 52
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#define RST_DDR7 53
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#define RST_DDR8 54
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#define RST_DDR9 55
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#define RST_DDR10 56
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#define RST_DDR11 57
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#define RST_DDR12 58
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#define RST_DDR13 59
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#define RST_DDR14 60
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#define RST_DDR15 61
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#define RST_BAR 62
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#define RST_K2K 63
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#define RST_CC_SYS_X1Y1 64
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#define RST_CC_SYS_X1Y2 65
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#define RST_CC_SYS_X1Y3 66
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#define RST_CC_SYS_X1Y4 67
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#define RST_CC_SYS_X0Y1 68
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#define RST_CC_SYS_X0Y2 69
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#define RST_CC_SYS_X0Y3 70
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#define RST_CC_SYS_X0Y4 71
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#define RST_SC_X1Y1 80
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#define RST_SC_X1Y2 81
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#define RST_SC_X1Y3 82
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#define RST_SC_X1Y4 83
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#define RST_SC_X0Y1 84
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#define RST_SC_X0Y2 85
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#define RST_SC_X0Y3 86
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#define RST_SC_X0Y4 87
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#define RST_RP_CLUSTER_X1Y1_S0 160
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#define RST_RP_CLUSTER_X1Y1_S1 161
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#define RST_RP_CLUSTER_X1Y2_S0 162
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#define RST_RP_CLUSTER_X1Y2_S1 163
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#define RST_RP_CLUSTER_X1Y3_S0 164
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#define RST_RP_CLUSTER_X1Y3_S1 165
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#define RST_RP_CLUSTER_X1Y4_S0 166
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#define RST_RP_CLUSTER_X1Y4_S1 167
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#define RST_RP_CLUSTER_X0Y1_W0 168
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#define RST_RP_CLUSTER_X0Y1_W1 169
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#define RST_RP_CLUSTER_X0Y2_W0 170
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#define RST_RP_CLUSTER_X0Y2_W1 171
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#define RST_RP_CLUSTER_X0Y3_W0 172
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#define RST_RP_CLUSTER_X0Y3_W1 173
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#define RST_RP_CLUSTER_X0Y4_W0 174
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#define RST_RP_CLUSTER_X0Y4_W1 175
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#define RST_TPSYS_X1Y1 180
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#define RST_TPSYS_X1Y2 181
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#define RST_TPSYS_X1Y3 182
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#define RST_TPSYS_X1Y4 183
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#define RST_TPSYS_X0Y1 184
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#define RST_TPSYS_X0Y2 185
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#define RST_TPSYS_X0Y3 186
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#define RST_TPSYS_X0Y4 187
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#define RST_SPACC 188
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#define RST_PKA 189
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#define RST_SE_TRNG 190
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#define RST_SE_DBG 191
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#define RST_SE_FAB_FW 192
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#define RST_SE_CTRL 193
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#define RST_MAILBOX0 194
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#define RST_MAILBOX1 195
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#define RST_MAILBOX2 196
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#define RST_MAILBOX3 197
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#define RST_INTC0 198
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#define RST_INTC1 199
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#define RST_INTC2 200
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#define RST_INTC3 201
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#endif /* _DT_BINDINGS_SG2044_RESET_H */
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