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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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39539df543
Add ethernet GMAC device node for the sg2042. Tested-by: Han Gao <rabenda.cn@gmail.com> Link: https://lore.kernel.org/r/20250708064627.509363-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
661 lines
19 KiB
Text
661 lines
19 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
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#include <dt-bindings/clock/sophgo,sg2042-pll.h>
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#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/pinctrl-sg2042.h>
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#include <dt-bindings/reset/sophgo,sg2042-reset.h>
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#include "sg2042-cpus.dtsi"
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/ {
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compatible = "sophgo,sg2042";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-noncoherent;
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aliases {
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serial0 = &uart0;
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};
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cgi_main: oscillator0 {
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compatible = "fixed-clock";
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clock-output-names = "cgi_main";
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#clock-cells = <0>;
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};
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cgi_dpll0: oscillator1 {
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compatible = "fixed-clock";
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clock-output-names = "cgi_dpll0";
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#clock-cells = <0>;
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};
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cgi_dpll1: oscillator2 {
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compatible = "fixed-clock";
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clock-output-names = "cgi_dpll1";
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#clock-cells = <0>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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ranges;
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i2c0: i2c@7030005000 {
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compatible = "snps,designware-i2c";
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reg = <0x70 0x30005000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_I2C>;
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clock-names = "ref";
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clock-frequency = <100000>;
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interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@7030006000 {
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compatible = "snps,designware-i2c";
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reg = <0x70 0x30006000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_I2C>;
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clock-names = "ref";
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clock-frequency = <100000>;
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interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_I2C1>;
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status = "disabled";
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};
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i2c2: i2c@7030007000 {
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compatible = "snps,designware-i2c";
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reg = <0x70 0x30007000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_I2C>;
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clock-names = "ref";
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clock-frequency = <100000>;
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interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_I2C2>;
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status = "disabled";
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};
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i2c3: i2c@7030008000 {
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compatible = "snps,designware-i2c";
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reg = <0x70 0x30008000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_I2C>;
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clock-names = "ref";
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clock-frequency = <100000>;
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interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_I2C3>;
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status = "disabled";
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};
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gpio0: gpio@7030009000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x70 0x30009000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_GPIO>,
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<&clkgen GATE_CLK_GPIO_DB>;
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clock-names = "bus", "db";
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port0a: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio1: gpio@703000a000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x70 0x3000a000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_GPIO>,
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<&clkgen GATE_CLK_GPIO_DB>;
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clock-names = "bus", "db";
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port1a: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio2: gpio@703000b000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x70 0x3000b000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_GPIO>,
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<&clkgen GATE_CLK_GPIO_DB>;
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clock-names = "bus", "db";
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port2a: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <98 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pwm: pwm@703000c000 {
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compatible = "sophgo,sg2042-pwm";
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reg = <0x70 0x3000c000 0x0 0x20>;
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#pwm-cells = <3>;
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clocks = <&clkgen GATE_CLK_APB_PWM>;
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clock-names = "apb";
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resets = <&rstgen RST_PWM>;
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};
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pllclk: clock-controller@70300100c0 {
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compatible = "sophgo,sg2042-pll";
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reg = <0x70 0x300100c0 0x0 0x40>;
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clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
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clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
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#clock-cells = <1>;
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};
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msi: msi-controller@7030010304 {
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compatible = "sophgo,sg2042-msi";
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reg = <0x70 0x30010304 0x0 0x4>,
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<0x70 0x30010300 0x0 0x4>;
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reg-names = "clr", "doorbell";
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msi-controller;
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#msi-cells = <0>;
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msi-ranges = <&intc 64 IRQ_TYPE_LEVEL_HIGH 32>;
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};
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rpgate: clock-controller@7030010368 {
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compatible = "sophgo,sg2042-rpgate";
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reg = <0x70 0x30010368 0x0 0x98>;
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clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
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clock-names = "rpgate";
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#clock-cells = <1>;
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};
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pinctrl: pinctrl@7030011000 {
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compatible = "sophgo,sg2042-pinctrl";
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reg = <0x70 0x30011000 0x0 0x1000>;
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};
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clkgen: clock-controller@7030012000 {
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compatible = "sophgo,sg2042-clkgen";
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reg = <0x70 0x30012000 0x0 0x1000>;
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clocks = <&pllclk MPLL_CLK>,
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<&pllclk FPLL_CLK>,
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<&pllclk DPLL0_CLK>,
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<&pllclk DPLL1_CLK>;
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clock-names = "mpll",
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"fpll",
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"dpll0",
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"dpll1";
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#clock-cells = <1>;
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};
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clint_mswi: interrupt-controller@7094000000 {
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compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
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reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
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interrupts-extended = <&cpu0_intc 3>,
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<&cpu1_intc 3>,
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<&cpu2_intc 3>,
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<&cpu3_intc 3>,
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<&cpu4_intc 3>,
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<&cpu5_intc 3>,
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<&cpu6_intc 3>,
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<&cpu7_intc 3>,
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<&cpu8_intc 3>,
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<&cpu9_intc 3>,
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<&cpu10_intc 3>,
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<&cpu11_intc 3>,
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<&cpu12_intc 3>,
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<&cpu13_intc 3>,
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<&cpu14_intc 3>,
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<&cpu15_intc 3>,
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<&cpu16_intc 3>,
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<&cpu17_intc 3>,
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<&cpu18_intc 3>,
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<&cpu19_intc 3>,
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<&cpu20_intc 3>,
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<&cpu21_intc 3>,
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<&cpu22_intc 3>,
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<&cpu23_intc 3>,
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<&cpu24_intc 3>,
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<&cpu25_intc 3>,
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<&cpu26_intc 3>,
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<&cpu27_intc 3>,
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<&cpu28_intc 3>,
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<&cpu29_intc 3>,
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<&cpu30_intc 3>,
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<&cpu31_intc 3>,
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<&cpu32_intc 3>,
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<&cpu33_intc 3>,
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<&cpu34_intc 3>,
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<&cpu35_intc 3>,
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<&cpu36_intc 3>,
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<&cpu37_intc 3>,
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<&cpu38_intc 3>,
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<&cpu39_intc 3>,
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<&cpu40_intc 3>,
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<&cpu41_intc 3>,
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<&cpu42_intc 3>,
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<&cpu43_intc 3>,
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<&cpu44_intc 3>,
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<&cpu45_intc 3>,
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<&cpu46_intc 3>,
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<&cpu47_intc 3>,
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<&cpu48_intc 3>,
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<&cpu49_intc 3>,
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<&cpu50_intc 3>,
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<&cpu51_intc 3>,
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<&cpu52_intc 3>,
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<&cpu53_intc 3>,
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<&cpu54_intc 3>,
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<&cpu55_intc 3>,
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<&cpu56_intc 3>,
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<&cpu57_intc 3>,
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<&cpu58_intc 3>,
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<&cpu59_intc 3>,
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<&cpu60_intc 3>,
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<&cpu61_intc 3>,
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<&cpu62_intc 3>,
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<&cpu63_intc 3>;
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};
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clint_mtimer0: timer@70ac004000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu0_intc 7>,
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<&cpu1_intc 7>,
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<&cpu2_intc 7>,
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<&cpu3_intc 7>;
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};
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clint_mtimer1: timer@70ac014000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu4_intc 7>,
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<&cpu5_intc 7>,
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<&cpu6_intc 7>,
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<&cpu7_intc 7>;
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};
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clint_mtimer2: timer@70ac024000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu8_intc 7>,
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<&cpu9_intc 7>,
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<&cpu10_intc 7>,
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<&cpu11_intc 7>;
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};
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clint_mtimer3: timer@70ac034000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu12_intc 7>,
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<&cpu13_intc 7>,
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<&cpu14_intc 7>,
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<&cpu15_intc 7>;
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};
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clint_mtimer4: timer@70ac044000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu16_intc 7>,
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<&cpu17_intc 7>,
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<&cpu18_intc 7>,
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<&cpu19_intc 7>;
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};
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clint_mtimer5: timer@70ac054000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu20_intc 7>,
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<&cpu21_intc 7>,
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<&cpu22_intc 7>,
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<&cpu23_intc 7>;
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};
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clint_mtimer6: timer@70ac064000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu24_intc 7>,
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<&cpu25_intc 7>,
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<&cpu26_intc 7>,
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<&cpu27_intc 7>;
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};
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clint_mtimer7: timer@70ac074000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu28_intc 7>,
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<&cpu29_intc 7>,
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<&cpu30_intc 7>,
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<&cpu31_intc 7>;
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};
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clint_mtimer8: timer@70ac084000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu32_intc 7>,
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<&cpu33_intc 7>,
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<&cpu34_intc 7>,
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<&cpu35_intc 7>;
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};
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clint_mtimer9: timer@70ac094000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu36_intc 7>,
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<&cpu37_intc 7>,
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<&cpu38_intc 7>,
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<&cpu39_intc 7>;
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};
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clint_mtimer10: timer@70ac0a4000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu40_intc 7>,
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<&cpu41_intc 7>,
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<&cpu42_intc 7>,
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<&cpu43_intc 7>;
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};
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clint_mtimer11: timer@70ac0b4000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu44_intc 7>,
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<&cpu45_intc 7>,
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<&cpu46_intc 7>,
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<&cpu47_intc 7>;
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};
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clint_mtimer12: timer@70ac0c4000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu48_intc 7>,
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<&cpu49_intc 7>,
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<&cpu50_intc 7>,
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<&cpu51_intc 7>;
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};
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clint_mtimer13: timer@70ac0d4000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu52_intc 7>,
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<&cpu53_intc 7>,
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<&cpu54_intc 7>,
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<&cpu55_intc 7>;
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};
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clint_mtimer14: timer@70ac0e4000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu56_intc 7>,
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<&cpu57_intc 7>,
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<&cpu58_intc 7>,
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<&cpu59_intc 7>;
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};
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clint_mtimer15: timer@70ac0f4000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu60_intc 7>,
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<&cpu61_intc 7>,
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<&cpu62_intc 7>,
|
|
<&cpu63_intc 7>;
|
|
};
|
|
|
|
intc: interrupt-controller@7090000000 {
|
|
compatible = "sophgo,sg2042-plic", "thead,c900-plic";
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
|
|
interrupt-controller;
|
|
interrupts-extended =
|
|
<&cpu0_intc 11>, <&cpu0_intc 9>,
|
|
<&cpu1_intc 11>, <&cpu1_intc 9>,
|
|
<&cpu2_intc 11>, <&cpu2_intc 9>,
|
|
<&cpu3_intc 11>, <&cpu3_intc 9>,
|
|
<&cpu4_intc 11>, <&cpu4_intc 9>,
|
|
<&cpu5_intc 11>, <&cpu5_intc 9>,
|
|
<&cpu6_intc 11>, <&cpu6_intc 9>,
|
|
<&cpu7_intc 11>, <&cpu7_intc 9>,
|
|
<&cpu8_intc 11>, <&cpu8_intc 9>,
|
|
<&cpu9_intc 11>, <&cpu9_intc 9>,
|
|
<&cpu10_intc 11>, <&cpu10_intc 9>,
|
|
<&cpu11_intc 11>, <&cpu11_intc 9>,
|
|
<&cpu12_intc 11>, <&cpu12_intc 9>,
|
|
<&cpu13_intc 11>, <&cpu13_intc 9>,
|
|
<&cpu14_intc 11>, <&cpu14_intc 9>,
|
|
<&cpu15_intc 11>, <&cpu15_intc 9>,
|
|
<&cpu16_intc 11>, <&cpu16_intc 9>,
|
|
<&cpu17_intc 11>, <&cpu17_intc 9>,
|
|
<&cpu18_intc 11>, <&cpu18_intc 9>,
|
|
<&cpu19_intc 11>, <&cpu19_intc 9>,
|
|
<&cpu20_intc 11>, <&cpu20_intc 9>,
|
|
<&cpu21_intc 11>, <&cpu21_intc 9>,
|
|
<&cpu22_intc 11>, <&cpu22_intc 9>,
|
|
<&cpu23_intc 11>, <&cpu23_intc 9>,
|
|
<&cpu24_intc 11>, <&cpu24_intc 9>,
|
|
<&cpu25_intc 11>, <&cpu25_intc 9>,
|
|
<&cpu26_intc 11>, <&cpu26_intc 9>,
|
|
<&cpu27_intc 11>, <&cpu27_intc 9>,
|
|
<&cpu28_intc 11>, <&cpu28_intc 9>,
|
|
<&cpu29_intc 11>, <&cpu29_intc 9>,
|
|
<&cpu30_intc 11>, <&cpu30_intc 9>,
|
|
<&cpu31_intc 11>, <&cpu31_intc 9>,
|
|
<&cpu32_intc 11>, <&cpu32_intc 9>,
|
|
<&cpu33_intc 11>, <&cpu33_intc 9>,
|
|
<&cpu34_intc 11>, <&cpu34_intc 9>,
|
|
<&cpu35_intc 11>, <&cpu35_intc 9>,
|
|
<&cpu36_intc 11>, <&cpu36_intc 9>,
|
|
<&cpu37_intc 11>, <&cpu37_intc 9>,
|
|
<&cpu38_intc 11>, <&cpu38_intc 9>,
|
|
<&cpu39_intc 11>, <&cpu39_intc 9>,
|
|
<&cpu40_intc 11>, <&cpu40_intc 9>,
|
|
<&cpu41_intc 11>, <&cpu41_intc 9>,
|
|
<&cpu42_intc 11>, <&cpu42_intc 9>,
|
|
<&cpu43_intc 11>, <&cpu43_intc 9>,
|
|
<&cpu44_intc 11>, <&cpu44_intc 9>,
|
|
<&cpu45_intc 11>, <&cpu45_intc 9>,
|
|
<&cpu46_intc 11>, <&cpu46_intc 9>,
|
|
<&cpu47_intc 11>, <&cpu47_intc 9>,
|
|
<&cpu48_intc 11>, <&cpu48_intc 9>,
|
|
<&cpu49_intc 11>, <&cpu49_intc 9>,
|
|
<&cpu50_intc 11>, <&cpu50_intc 9>,
|
|
<&cpu51_intc 11>, <&cpu51_intc 9>,
|
|
<&cpu52_intc 11>, <&cpu52_intc 9>,
|
|
<&cpu53_intc 11>, <&cpu53_intc 9>,
|
|
<&cpu54_intc 11>, <&cpu54_intc 9>,
|
|
<&cpu55_intc 11>, <&cpu55_intc 9>,
|
|
<&cpu56_intc 11>, <&cpu56_intc 9>,
|
|
<&cpu57_intc 11>, <&cpu57_intc 9>,
|
|
<&cpu58_intc 11>, <&cpu58_intc 9>,
|
|
<&cpu59_intc 11>, <&cpu59_intc 9>,
|
|
<&cpu60_intc 11>, <&cpu60_intc 9>,
|
|
<&cpu61_intc 11>, <&cpu61_intc 9>,
|
|
<&cpu62_intc 11>, <&cpu62_intc 9>,
|
|
<&cpu63_intc 11>, <&cpu63_intc 9>;
|
|
riscv,ndev = <224>;
|
|
};
|
|
|
|
rstgen: reset-controller@7030013000 {
|
|
compatible = "sophgo,sg2042-reset";
|
|
reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
uart0: serial@7040000000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
|
|
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <500000000>;
|
|
clocks = <&clkgen GATE_CLK_UART_500M>,
|
|
<&clkgen GATE_CLK_APB_UART>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
resets = <&rstgen RST_UART0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@7040004000 {
|
|
compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
|
|
reg = <0x70 0x40004000 0x00 0x1000>;
|
|
clocks = <&clkgen GATE_CLK_APB_SPI>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
num-cs = <2>;
|
|
resets = <&rstgen RST_SPI0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@7040005000 {
|
|
compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
|
|
reg = <0x70 0x40005000 0x00 0x1000>;
|
|
clocks = <&clkgen GATE_CLK_APB_SPI>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
num-cs = <2>;
|
|
resets = <&rstgen RST_SPI1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac0: ethernet@7040026000 {
|
|
compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a";
|
|
reg = <0x70 0x40026000 0x0 0x4000>;
|
|
clocks = <&clkgen GATE_CLK_AXI_ETH0>,
|
|
<&clkgen GATE_CLK_PTP_REF_I_ETH0>,
|
|
<&clkgen GATE_CLK_TX_ETH0>;
|
|
clock-names = "stmmaceth", "ptp_ref", "tx";
|
|
dma-noncoherent;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <132 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
resets = <&rstgen RST_ETH0>;
|
|
reset-names = "stmmaceth";
|
|
snps,multicast-filter-bins = <0>;
|
|
snps,perfect-filter-entries = <1>;
|
|
snps,aal;
|
|
snps,tso;
|
|
snps,txpbl = <32>;
|
|
snps,rxpbl = <32>;
|
|
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
|
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
|
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
|
status = "disabled";
|
|
|
|
mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
gmac0_mtl_rx_setup: rx-queues-config {
|
|
snps,rx-queues-to-use = <8>;
|
|
queue0 {};
|
|
queue1 {};
|
|
queue2 {};
|
|
queue3 {};
|
|
queue4 {};
|
|
queue5 {};
|
|
queue6 {};
|
|
queue7 {};
|
|
};
|
|
|
|
gmac0_mtl_tx_setup: tx-queues-config {
|
|
snps,tx-queues-to-use = <8>;
|
|
queue0 {};
|
|
queue1 {};
|
|
queue2 {};
|
|
queue3 {};
|
|
queue4 {};
|
|
queue5 {};
|
|
queue6 {};
|
|
queue7 {};
|
|
};
|
|
|
|
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
|
snps,blen = <16 8 4 0 0 0 0>;
|
|
snps,wr_osr_lmt = <1>;
|
|
snps,rd_osr_lmt = <2>;
|
|
};
|
|
};
|
|
|
|
emmc: mmc@704002a000 {
|
|
compatible = "sophgo,sg2042-dwcmshc";
|
|
reg = <0x70 0x4002a000 0x0 0x1000>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clkgen GATE_CLK_EMMC_100M>,
|
|
<&clkgen GATE_CLK_AXI_EMMC>,
|
|
<&clkgen GATE_CLK_100K_EMMC>;
|
|
clock-names = "core",
|
|
"bus",
|
|
"timer";
|
|
status = "disabled";
|
|
};
|
|
|
|
sd: mmc@704002b000 {
|
|
compatible = "sophgo,sg2042-dwcmshc";
|
|
reg = <0x70 0x4002b000 0x0 0x1000>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clkgen GATE_CLK_SD_100M>,
|
|
<&clkgen GATE_CLK_AXI_SD>,
|
|
<&clkgen GATE_CLK_100K_SD>;
|
|
clock-names = "core",
|
|
"bus",
|
|
"timer";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|