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e595fa85db
Since riscv and arm architecture use different interrupt definitions, use a macro SOC_PERIPHERAL_IRQ mask this difference. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250430012654.235830-5-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
21 lines
499 B
Text
21 lines
499 B
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
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*/
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#include <dt-bindings/clock/sophgo,cv1800.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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soc {
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emmc: mmc@4300000 {
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compatible = "sophgo,cv1800b-dwcmshc";
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reg = <0x4300000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_AXI4_EMMC>,
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<&clk CLK_EMMC>;
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clock-names = "core", "bus";
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status = "disabled";
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};
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};
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};
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