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9b181f4a95
The existing PolarFire SoC devicetrees all use root port instance 1, update the reg properties in PCIe nodes to use the new format that specifies the instance in use. Failing to do so would still work but produces warnings: mpfs-icicle-kit.dtb: pcie@3000000000: reg: [[48, 0, 0, 134217728], [0, 1124073472, 0, 65536]] is too short mpfs-icicle-kit.dtb: pcie@3000000000: reg-names: ['cfg', 'apb'] is too short Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- CC: Conor Dooley <conor@kernel.org> CC: Daire McNamara <daire.mcnamara@microchip.com> CC: valentina.fernandezalanis@microchip.com CC: Rob Herring <robh@kernel.org> CC: Krzysztof Kozlowski <krzk+dt@kernel.org> CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org CC: linux-kernel@vger.kernel.org
72 lines
2 KiB
Text
72 lines
2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/ {
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compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
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"microchip,mpfs";
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core_pwm0: pwm@40000000 {
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compatible = "microchip,corepwm-rtl-v4";
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reg = <0x0 0x40000000 0x0 0xF0>;
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microchip,sync-update-mask = /bits/ 32 <0>;
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#pwm-cells = <3>;
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clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
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status = "disabled";
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};
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i2c2: i2c@40000200 {
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compatible = "microchip,corei2c-rtl-v7";
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reg = <0x0 0x40000200 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
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interrupt-parent = <&plic>;
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interrupts = <122>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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pcie: pcie@3000000000 {
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compatible = "microchip,pcie-host-1.0";
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#address-cells = <0x3>;
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#interrupt-cells = <0x1>;
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#size-cells = <0x2>;
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device_type = "pci";
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reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
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<0x0 0x4300a000 0x0 0x2000>;
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reg-names = "cfg", "bridge", "ctrl";
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bus-range = <0x0 0x7f>;
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interrupt-parent = <&plic>;
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interrupts = <119>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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interrupt-map-mask = <0 0 0 7>;
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clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
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clock-names = "fic1", "fic3";
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ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
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dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
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msi-parent = <&pcie>;
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msi-controller;
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status = "disabled";
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pcie_intc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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refclk_ccc: cccrefclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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&ccc_nw {
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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status = "okay";
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};
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