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aca95fb6bb
This adds support for Microwatt systems with more than one core, and updates the device tree for a 2-core version. The secondary CPUs are started and sent to spin in __secondary_hold very early on, in the platform probe function. The reason for doing this is so that they are there when smp_release_cpus() gets called, which is before the platform init_smp function or even the platform setup_arch function gets called. Note that having two CPUs in the device tree doesn't preclude operation with only one CPU. The SYSCON_CPU_CTRL register has a read-only field which indicates the number of CPU cores, so microwatt_init_smp() will only start as many CPU cores as are present in the system, and any extra CPU device-tree nodes will just be ignored. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/Z5xt8aooKyXZv6Kf@thinks.paulus.ozlabs.org
80 lines
1.7 KiB
C
80 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* SMP support functions for Microwatt
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* Copyright 2025 Paul Mackerras <paulus@ozlabs.org>
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*/
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#include <linux/kernel.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/early_ioremap.h>
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#include <asm/ppc-opcode.h>
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#include <asm/reg.h>
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#include <asm/smp.h>
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#include <asm/xics.h>
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#include "microwatt.h"
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static void __init microwatt_smp_probe(void)
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{
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xics_smp_probe();
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}
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static void microwatt_smp_setup_cpu(int cpu)
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{
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if (cpu != 0)
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xics_setup_cpu();
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}
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static struct smp_ops_t microwatt_smp_ops = {
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.probe = microwatt_smp_probe,
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.message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
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.kick_cpu = smp_generic_kick_cpu,
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.setup_cpu = microwatt_smp_setup_cpu,
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};
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/* XXX get from device tree */
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#define SYSCON_BASE 0xc0000000
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#define SYSCON_LENGTH 0x100
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#define SYSCON_CPU_CTRL 0x58
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void __init microwatt_init_smp(void)
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{
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volatile unsigned char __iomem *syscon;
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int ncpus;
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int timeout;
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syscon = early_ioremap(SYSCON_BASE, SYSCON_LENGTH);
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if (syscon == NULL) {
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pr_err("Failed to map SYSCON\n");
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return;
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}
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ncpus = (readl(syscon + SYSCON_CPU_CTRL) >> 8) & 0xff;
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if (ncpus < 2)
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goto out;
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smp_ops = µwatt_smp_ops;
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/*
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* Write two instructions at location 0:
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* mfspr r3, PIR
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* b __secondary_hold
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*/
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*(unsigned int *)KERNELBASE = PPC_RAW_MFSPR(3, SPRN_PIR);
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*(unsigned int *)(KERNELBASE+4) = PPC_RAW_BRANCH(&__secondary_hold - (char *)(KERNELBASE+4));
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/* enable the other CPUs, they start at location 0 */
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writel((1ul << ncpus) - 1, syscon + SYSCON_CPU_CTRL);
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timeout = 10000;
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while (!__secondary_hold_acknowledge) {
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if (--timeout == 0)
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break;
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barrier();
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}
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out:
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early_iounmap((void *)syscon, SYSCON_LENGTH);
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}
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