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IBM Cell Blades used the Cell processor and the "blade" server form factor. They were sold as models QS20, QS21 & QS22 from roughly 2006 to 2012 [1]. They were used in a few supercomputers (eg. Roadrunner) that have since been dismantled, and were not that widely used otherwise. Until recently I still had a working QS22, which meant I was able to keep the platform support working, but unfortunately that machine has now died. I'm not aware of any users. If there is a user that wants to keep the upstream support working, we can look at bringing some of the code back as appropriate. See previous discussion at [2]. Remove the top-level config symbol PPC_IBM_CELL_BLADE, and then the dependent symbols PPC_CELL_NATIVE, PPC_CELL_COMMON, CBE_RAS, PPC_IBM_CELL_RESETBUTTON, PPC_IBM_CELL_POWERBUTTON, CBE_THERM, and AXON_MSI. Then remove the associated C files and headers, and trim unused header content (some is shared with PS3). Note that PPC_CELL_COMMON sounds like it would build code shared with PS3, but it does not. It's a relic from when code was shared between the Blade support and QPACE support. Most of the primary authors already have CREDITS entries, with the exception of Christian, so add one for him. [1]: https://www.theregister.com/2011/06/28/ibm_kills_qs22_blade [2]: https://lore.kernel.org/linuxppc-dev/60581044-df82-40ad-b94c-56468007a93e@app.fastmail.com Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jeremy Kerr <jk@ozlabs.org> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20241218105523.416573-1-mpe@ellerman.id.au
221 lines
5 KiB
C
221 lines
5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Defines an spu hypervisor abstraction layer.
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*
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* Copyright 2006 Sony Corp.
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*/
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#if !defined(_SPU_PRIV1_H)
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#define _SPU_PRIV1_H
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#if defined(__KERNEL__)
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#include <linux/types.h>
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struct spu;
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struct spu_context;
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/* access to priv1 registers */
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struct spu_priv1_ops {
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void (*int_mask_and) (struct spu *spu, int class, u64 mask);
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void (*int_mask_or) (struct spu *spu, int class, u64 mask);
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void (*int_mask_set) (struct spu *spu, int class, u64 mask);
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u64 (*int_mask_get) (struct spu *spu, int class);
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void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
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u64 (*int_stat_get) (struct spu *spu, int class);
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void (*cpu_affinity_set) (struct spu *spu, int cpu);
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u64 (*mfc_dar_get) (struct spu *spu);
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u64 (*mfc_dsisr_get) (struct spu *spu);
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void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
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void (*mfc_sdr_setup) (struct spu *spu);
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void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
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u64 (*mfc_sr1_get) (struct spu *spu);
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void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
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u64 (*mfc_tclass_id_get) (struct spu *spu);
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void (*tlb_invalidate) (struct spu *spu);
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void (*resource_allocation_groupID_set) (struct spu *spu, u64 id);
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u64 (*resource_allocation_groupID_get) (struct spu *spu);
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void (*resource_allocation_enable_set) (struct spu *spu, u64 enable);
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u64 (*resource_allocation_enable_get) (struct spu *spu);
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};
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extern const struct spu_priv1_ops* spu_priv1_ops;
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static inline void
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spu_int_mask_and (struct spu *spu, int class, u64 mask)
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{
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spu_priv1_ops->int_mask_and(spu, class, mask);
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}
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static inline void
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spu_int_mask_or (struct spu *spu, int class, u64 mask)
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{
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spu_priv1_ops->int_mask_or(spu, class, mask);
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}
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static inline void
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spu_int_mask_set (struct spu *spu, int class, u64 mask)
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{
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spu_priv1_ops->int_mask_set(spu, class, mask);
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}
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static inline u64
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spu_int_mask_get (struct spu *spu, int class)
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{
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return spu_priv1_ops->int_mask_get(spu, class);
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}
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static inline void
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spu_int_stat_clear (struct spu *spu, int class, u64 stat)
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{
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spu_priv1_ops->int_stat_clear(spu, class, stat);
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}
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static inline u64
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spu_int_stat_get (struct spu *spu, int class)
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{
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return spu_priv1_ops->int_stat_get (spu, class);
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}
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static inline void
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spu_cpu_affinity_set (struct spu *spu, int cpu)
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{
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spu_priv1_ops->cpu_affinity_set(spu, cpu);
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}
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static inline u64
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spu_mfc_dar_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_dar_get(spu);
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}
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static inline u64
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spu_mfc_dsisr_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_dsisr_get(spu);
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}
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static inline void
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spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
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{
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spu_priv1_ops->mfc_dsisr_set(spu, dsisr);
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}
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static inline void
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spu_mfc_sdr_setup (struct spu *spu)
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{
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spu_priv1_ops->mfc_sdr_setup(spu);
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}
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static inline void
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spu_mfc_sr1_set (struct spu *spu, u64 sr1)
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{
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spu_priv1_ops->mfc_sr1_set(spu, sr1);
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}
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static inline u64
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spu_mfc_sr1_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_sr1_get(spu);
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}
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static inline void
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spu_mfc_tclass_id_set (struct spu *spu, u64 tclass_id)
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{
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spu_priv1_ops->mfc_tclass_id_set(spu, tclass_id);
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}
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static inline u64
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spu_mfc_tclass_id_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_tclass_id_get(spu);
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}
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static inline void
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spu_tlb_invalidate (struct spu *spu)
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{
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spu_priv1_ops->tlb_invalidate(spu);
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}
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static inline void
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spu_resource_allocation_groupID_set (struct spu *spu, u64 id)
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{
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spu_priv1_ops->resource_allocation_groupID_set(spu, id);
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}
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static inline u64
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spu_resource_allocation_groupID_get (struct spu *spu)
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{
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return spu_priv1_ops->resource_allocation_groupID_get(spu);
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}
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static inline void
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spu_resource_allocation_enable_set (struct spu *spu, u64 enable)
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{
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spu_priv1_ops->resource_allocation_enable_set(spu, enable);
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}
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static inline u64
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spu_resource_allocation_enable_get (struct spu *spu)
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{
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return spu_priv1_ops->resource_allocation_enable_get(spu);
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}
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/* spu management abstraction */
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struct spu_management_ops {
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int (*enumerate_spus)(int (*fn)(void *data));
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int (*create_spu)(struct spu *spu, void *data);
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int (*destroy_spu)(struct spu *spu);
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void (*enable_spu)(struct spu_context *ctx);
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void (*disable_spu)(struct spu_context *ctx);
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int (*init_affinity)(void);
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};
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extern const struct spu_management_ops* spu_management_ops;
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static inline int
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spu_enumerate_spus (int (*fn)(void *data))
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{
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return spu_management_ops->enumerate_spus(fn);
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}
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static inline int
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spu_create_spu (struct spu *spu, void *data)
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{
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return spu_management_ops->create_spu(spu, data);
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}
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static inline int
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spu_destroy_spu (struct spu *spu)
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{
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return spu_management_ops->destroy_spu(spu);
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}
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static inline int
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spu_init_affinity (void)
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{
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return spu_management_ops->init_affinity();
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}
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static inline void
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spu_enable_spu (struct spu_context *ctx)
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{
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spu_management_ops->enable_spu(ctx);
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}
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static inline void
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spu_disable_spu (struct spu_context *ctx)
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{
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spu_management_ops->disable_spu(ctx);
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}
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/*
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* The declarations following are put here for convenience
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* and only intended to be used by the platform setup code.
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*/
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extern const struct spu_management_ops spu_management_of_ops;
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#endif /* __KERNEL__ */
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#endif
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