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91428ca932
Because of the way the _PAGE_READ is handled in the parisc PTE, an access interruption is not generated when the kernel reads from a region where the _PAGE_READ is zero. The current code was written assuming read access faults would also occur in the kernel. This change adds user access checks to raw_copy_from_user(). The prober_user() define checks whether user code has read access to a virtual address. Note that page faults are not handled in the exception support for the probe instruction. For this reason, we precede the probe by a ldb access check. Signed-off-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Helge Deller <deller@gmx.de> Cc: stable@vger.kernel.org # v5.12+
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __PARISC_SPECIAL_INSNS_H
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#define __PARISC_SPECIAL_INSNS_H
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#define lpa(va) ({ \
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unsigned long pa; \
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__asm__ __volatile__( \
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"copy %%r0,%0\n" \
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"8:\tlpa %%r0(%1),%0\n" \
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"9:\n" \
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ASM_EXCEPTIONTABLE_ENTRY(8b, 9b, \
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"or %%r0,%%r0,%%r0") \
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: "=&r" (pa) \
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: "r" (va) \
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: "memory" \
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); \
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pa; \
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})
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#define lpa_user(va) ({ \
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unsigned long pa; \
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__asm__ __volatile__( \
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"copy %%r0,%0\n" \
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"8:\tlpa %%r0(%%sr3,%1),%0\n" \
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"9:\n" \
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ASM_EXCEPTIONTABLE_ENTRY(8b, 9b, \
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"or %%r0,%%r0,%%r0") \
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: "=&r" (pa) \
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: "r" (va) \
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: "memory" \
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); \
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pa; \
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})
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/**
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* prober_user() - Probe user read access
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* @sr: Space regster.
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* @va: Virtual address.
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*
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* Return: Non-zero if address is accessible.
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*
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* Due to the way _PAGE_READ is handled in TLB entries, we need
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* a special check to determine whether a user address is accessible.
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* The ldb instruction does the initial access check. If it is
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* successful, the probe instruction checks user access rights.
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*/
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#define prober_user(sr, va) ({ \
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unsigned long read_allowed; \
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__asm__ __volatile__( \
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"copy %%r0,%0\n" \
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"8:\tldb 0(%%sr%1,%2),%%r0\n" \
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"\tproberi (%%sr%1,%2),%3,%0\n" \
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"9:\n" \
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ASM_EXCEPTIONTABLE_ENTRY(8b, 9b, \
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"or %%r0,%%r0,%%r0") \
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: "=&r" (read_allowed) \
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: "i" (sr), "r" (va), "i" (PRIV_USER) \
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: "memory" \
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); \
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read_allowed; \
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})
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#define CR_EIEM 15 /* External Interrupt Enable Mask */
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#define CR_CR16 16 /* CR16 Interval Timer */
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#define CR_EIRR 23 /* External Interrupt Request Register */
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#define mfctl(reg) ({ \
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unsigned long cr; \
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__asm__ __volatile__( \
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"mfctl %1,%0" : \
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"=r" (cr) : "i" (reg) \
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); \
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cr; \
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})
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#define mtctl(gr, cr) \
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__asm__ __volatile__("mtctl %0,%1" \
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: /* no outputs */ \
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: "r" (gr), "i" (cr) : "memory")
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#define get_eiem() mfctl(CR_EIEM)
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#define set_eiem(val) mtctl(val, CR_EIEM)
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#define mfsp(reg) ({ \
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unsigned long cr; \
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__asm__ __volatile__( \
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"mfsp %%sr%1,%0" \
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: "=r" (cr) : "i"(reg) \
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); \
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cr; \
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})
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#define mtsp(val, cr) \
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{ if (__builtin_constant_p(val) && ((val) == 0)) \
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__asm__ __volatile__("mtsp %%r0,%0" : : "i" (cr) : "memory"); \
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else \
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__asm__ __volatile__("mtsp %0,%1" \
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: /* no outputs */ \
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: "r" (val), "i" (cr) : "memory"); }
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#endif /* __PARISC_SPECIAL_INSNS_H */
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