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0c4a6e79ef
According to the OpenRISC architecture manual, the dcache and icache may not be present. When these caches are present, the invalidate and flush registers may be absent. The current implementation does not perform checks to verify their presence before utilizing cache registers, or invalidating and flushing cache blocks. Introduce new functions to detect the presence of cache components and related special-purpose registers. There are a few places where a range of addresses have to be flushed or invalidated and the implementation is duplicated. Introduce new utility functions and macros that generalize this implementation and reduce duplication. Signed-off-by: Sahil Siddiq <sahilcdq0@gmail.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
99 lines
2.5 KiB
C
99 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* OpenRISC cache.c
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* Modifications for the OpenRISC architecture:
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* Copyright (C) 2015 Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
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*/
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#include <asm/spr.h>
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#include <asm/spr_defs.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/cpuinfo.h>
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#include <asm/tlbflush.h>
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/*
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* Check if the cache component exists.
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*/
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bool cpu_cache_is_present(const unsigned int cache_type)
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{
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unsigned long upr = mfspr(SPR_UPR);
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unsigned long mask = SPR_UPR_UP | cache_type;
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return !((upr & mask) ^ mask);
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}
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static __always_inline void cache_loop(unsigned long paddr, unsigned long end,
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const unsigned short reg, const unsigned int cache_type)
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{
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if (!cpu_cache_is_present(cache_type))
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return;
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while (paddr < end) {
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mtspr(reg, paddr);
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paddr += L1_CACHE_BYTES;
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}
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}
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static __always_inline void cache_loop_page(struct page *page, const unsigned short reg,
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const unsigned int cache_type)
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{
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unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
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unsigned long end = paddr + PAGE_SIZE;
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paddr &= ~(L1_CACHE_BYTES - 1);
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cache_loop(paddr, end, reg, cache_type);
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}
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void local_dcache_page_flush(struct page *page)
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{
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cache_loop_page(page, SPR_DCBFR, SPR_UPR_DCP);
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}
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EXPORT_SYMBOL(local_dcache_page_flush);
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void local_icache_page_inv(struct page *page)
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{
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cache_loop_page(page, SPR_ICBIR, SPR_UPR_ICP);
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}
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EXPORT_SYMBOL(local_icache_page_inv);
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void local_dcache_range_flush(unsigned long start, unsigned long end)
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{
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cache_loop(start, end, SPR_DCBFR, SPR_UPR_DCP);
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}
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void local_dcache_range_inv(unsigned long start, unsigned long end)
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{
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cache_loop(start, end, SPR_DCBIR, SPR_UPR_DCP);
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}
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void local_icache_range_inv(unsigned long start, unsigned long end)
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{
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cache_loop(start, end, SPR_ICBIR, SPR_UPR_ICP);
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}
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void update_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t *pte)
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{
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unsigned long pfn = pte_val(*pte) >> PAGE_SHIFT;
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struct folio *folio = page_folio(pfn_to_page(pfn));
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int dirty = !test_and_set_bit(PG_dc_clean, &folio->flags);
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/*
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* Since icaches do not snoop for updated data on OpenRISC, we
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* must write back and invalidate any dirty pages manually. We
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* can skip data pages, since they will not end up in icaches.
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*/
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if ((vma->vm_flags & VM_EXEC) && dirty) {
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unsigned int nr = folio_nr_pages(folio);
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while (nr--)
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sync_icache_dcache(folio_page(folio, nr));
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}
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}
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