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4e6d24a309
Add cacheinfo support for OpenRISC. Currently, a few CPU cache attributes pertaining to OpenRISC processors are exposed along with other unrelated CPU attributes in the procfs file system (/proc/cpuinfo). However, a few cache attributes remain unexposed. Provide a mechanism that the generic cacheinfo infrastructure can employ to expose these attributes via the sysfs file system. These attributes can then be exposed in /sys/devices/system/cpu/cpuX/cache/indexN. Move the implementation to pull cache attributes from the processor's registers from arch/openrisc/kernel/setup.c with a few modifications. This implementation is based on similar work done for MIPS and LoongArch. Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf Signed-off-by: Sahil Siddiq <sahilcdq0@gmail.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* OpenRISC cacheinfo support
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*
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* Based on work done for MIPS and LoongArch. All original copyrights
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* apply as per the original source declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) 2025 Sahil Siddiq <sahilcdq@proton.me>
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*/
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#include <linux/cacheinfo.h>
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#include <asm/cpuinfo.h>
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#include <asm/spr.h>
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#include <asm/spr_defs.h>
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static inline void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type,
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unsigned int level, struct cache_desc *cache, int cpu)
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{
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this_leaf->type = type;
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this_leaf->level = level;
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this_leaf->coherency_line_size = cache->block_size;
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this_leaf->number_of_sets = cache->sets;
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this_leaf->ways_of_associativity = cache->ways;
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this_leaf->size = cache->size;
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cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map);
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}
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int init_cache_level(unsigned int cpu)
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{
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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int leaves = 0, levels = 0;
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unsigned long upr = mfspr(SPR_UPR);
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unsigned long iccfgr, dccfgr;
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if (!(upr & SPR_UPR_UP)) {
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printk(KERN_INFO
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"-- no UPR register... unable to detect configuration\n");
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return -ENOENT;
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}
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if (cpu_cache_is_present(SPR_UPR_DCP)) {
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dccfgr = mfspr(SPR_DCCFGR);
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cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
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cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
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cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
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cpuinfo->dcache.size =
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cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
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leaves += 1;
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printk(KERN_INFO
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"-- dcache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
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cpuinfo->dcache.size, cpuinfo->dcache.block_size,
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cpuinfo->dcache.sets, cpuinfo->dcache.ways);
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} else
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printk(KERN_INFO "-- dcache disabled\n");
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if (cpu_cache_is_present(SPR_UPR_ICP)) {
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iccfgr = mfspr(SPR_ICCFGR);
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cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
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cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
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cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
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cpuinfo->icache.size =
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cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
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leaves += 1;
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printk(KERN_INFO
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"-- icache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
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cpuinfo->icache.size, cpuinfo->icache.block_size,
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cpuinfo->icache.sets, cpuinfo->icache.ways);
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} else
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printk(KERN_INFO "-- icache disabled\n");
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if (!leaves)
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return -ENOENT;
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levels = 1;
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this_cpu_ci->num_leaves = leaves;
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this_cpu_ci->num_levels = levels;
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return 0;
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}
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int populate_cache_leaves(unsigned int cpu)
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{
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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struct cacheinfo *this_leaf = this_cpu_ci->info_list;
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int level = 1;
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if (cpu_cache_is_present(SPR_UPR_DCP)) {
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ci_leaf_init(this_leaf, CACHE_TYPE_DATA, level, &cpuinfo->dcache, cpu);
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this_leaf->attributes = ((mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS) >> 8) ?
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CACHE_WRITE_BACK : CACHE_WRITE_THROUGH;
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this_leaf++;
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}
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if (cpu_cache_is_present(SPR_UPR_ICP))
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ci_leaf_init(this_leaf, CACHE_TYPE_INST, level, &cpuinfo->icache, cpu);
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this_cpu_ci->cpu_map_populated = true;
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return 0;
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}
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