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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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c1474bb0b7
The branch instructions beq, bne, blt, bge, bltu, bgeu and jirl belong to the format reg2i16, but the sequence of oprand is different for the instruction jirl. So adjust the parameter order of emit_jirl() to make it more readable correspond with the Instruction Set Architecture manual. Here are the instruction formats: beq rj, rd, offs16 bne rj, rd, offs16 blt rj, rd, offs16 bge rj, rd, offs16 bltu rj, rd, offs16 bgeu rj, rd, offs16 jirl rd, rj, offs16 Link: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#branch-instructions Suggested-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
338 lines
7.4 KiB
C
338 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/sizes.h>
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#include <linux/uaccess.h>
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#include <asm/cacheflush.h>
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#include <asm/inst.h>
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static DEFINE_RAW_SPINLOCK(patch_lock);
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void simu_pc(struct pt_regs *regs, union loongarch_instruction insn)
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{
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unsigned long pc = regs->csr_era;
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unsigned int rd = insn.reg1i20_format.rd;
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unsigned int imm = insn.reg1i20_format.immediate;
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if (pc & 3) {
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pr_warn("%s: invalid pc 0x%lx\n", __func__, pc);
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return;
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}
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switch (insn.reg1i20_format.opcode) {
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case pcaddi_op:
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regs->regs[rd] = pc + sign_extend64(imm << 2, 21);
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break;
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case pcaddu12i_op:
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regs->regs[rd] = pc + sign_extend64(imm << 12, 31);
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break;
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case pcaddu18i_op:
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regs->regs[rd] = pc + sign_extend64(imm << 18, 37);
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break;
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case pcalau12i_op:
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regs->regs[rd] = pc + sign_extend64(imm << 12, 31);
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regs->regs[rd] &= ~((1 << 12) - 1);
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break;
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default:
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pr_info("%s: unknown opcode\n", __func__);
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return;
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}
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regs->csr_era += LOONGARCH_INSN_SIZE;
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}
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void simu_branch(struct pt_regs *regs, union loongarch_instruction insn)
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{
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unsigned int imm, imm_l, imm_h, rd, rj;
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unsigned long pc = regs->csr_era;
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if (pc & 3) {
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pr_warn("%s: invalid pc 0x%lx\n", __func__, pc);
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return;
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}
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imm_l = insn.reg0i26_format.immediate_l;
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imm_h = insn.reg0i26_format.immediate_h;
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switch (insn.reg0i26_format.opcode) {
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case b_op:
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regs->csr_era = pc + sign_extend64((imm_h << 16 | imm_l) << 2, 27);
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return;
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case bl_op:
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regs->csr_era = pc + sign_extend64((imm_h << 16 | imm_l) << 2, 27);
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regs->regs[1] = pc + LOONGARCH_INSN_SIZE;
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return;
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}
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imm_l = insn.reg1i21_format.immediate_l;
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imm_h = insn.reg1i21_format.immediate_h;
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rj = insn.reg1i21_format.rj;
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switch (insn.reg1i21_format.opcode) {
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case beqz_op:
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if (regs->regs[rj] == 0)
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regs->csr_era = pc + sign_extend64((imm_h << 16 | imm_l) << 2, 22);
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else
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regs->csr_era = pc + LOONGARCH_INSN_SIZE;
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return;
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case bnez_op:
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if (regs->regs[rj] != 0)
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regs->csr_era = pc + sign_extend64((imm_h << 16 | imm_l) << 2, 22);
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else
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regs->csr_era = pc + LOONGARCH_INSN_SIZE;
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return;
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}
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imm = insn.reg2i16_format.immediate;
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rj = insn.reg2i16_format.rj;
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rd = insn.reg2i16_format.rd;
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switch (insn.reg2i16_format.opcode) {
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case beq_op:
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if (regs->regs[rj] == regs->regs[rd])
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regs->csr_era = pc + sign_extend64(imm << 2, 17);
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else
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regs->csr_era = pc + LOONGARCH_INSN_SIZE;
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break;
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case bne_op:
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if (regs->regs[rj] != regs->regs[rd])
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regs->csr_era = pc + sign_extend64(imm << 2, 17);
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else
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regs->csr_era = pc + LOONGARCH_INSN_SIZE;
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break;
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case blt_op:
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if ((long)regs->regs[rj] < (long)regs->regs[rd])
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regs->csr_era = pc + sign_extend64(imm << 2, 17);
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else
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regs->csr_era = pc + LOONGARCH_INSN_SIZE;
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break;
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case bge_op:
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if ((long)regs->regs[rj] >= (long)regs->regs[rd])
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regs->csr_era = pc + sign_extend64(imm << 2, 17);
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else
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regs->csr_era = pc + LOONGARCH_INSN_SIZE;
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break;
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case bltu_op:
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if (regs->regs[rj] < regs->regs[rd])
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regs->csr_era = pc + sign_extend64(imm << 2, 17);
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else
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regs->csr_era = pc + LOONGARCH_INSN_SIZE;
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break;
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case bgeu_op:
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if (regs->regs[rj] >= regs->regs[rd])
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regs->csr_era = pc + sign_extend64(imm << 2, 17);
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else
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regs->csr_era = pc + LOONGARCH_INSN_SIZE;
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break;
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case jirl_op:
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regs->csr_era = regs->regs[rj] + sign_extend64(imm << 2, 17);
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regs->regs[rd] = pc + LOONGARCH_INSN_SIZE;
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break;
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default:
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pr_info("%s: unknown opcode\n", __func__);
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return;
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}
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}
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bool insns_not_supported(union loongarch_instruction insn)
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{
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switch (insn.reg3_format.opcode) {
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case amswapw_op ... ammindbdu_op:
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pr_notice("atomic memory access instructions are not supported\n");
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return true;
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}
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switch (insn.reg2i14_format.opcode) {
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case llw_op:
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case lld_op:
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case scw_op:
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case scd_op:
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pr_notice("ll and sc instructions are not supported\n");
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return true;
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}
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switch (insn.reg1i21_format.opcode) {
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case bceqz_op:
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pr_notice("bceqz and bcnez instructions are not supported\n");
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return true;
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}
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return false;
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}
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bool insns_need_simulation(union loongarch_instruction insn)
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{
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if (is_pc_ins(&insn))
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return true;
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if (is_branch_ins(&insn))
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return true;
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return false;
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}
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void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs)
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{
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if (is_pc_ins(&insn))
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simu_pc(regs, insn);
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else if (is_branch_ins(&insn))
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simu_branch(regs, insn);
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}
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int larch_insn_read(void *addr, u32 *insnp)
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{
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int ret;
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u32 val;
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ret = copy_from_kernel_nofault(&val, addr, LOONGARCH_INSN_SIZE);
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if (!ret)
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*insnp = val;
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return ret;
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}
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int larch_insn_write(void *addr, u32 insn)
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{
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int ret;
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unsigned long flags = 0;
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raw_spin_lock_irqsave(&patch_lock, flags);
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ret = copy_to_kernel_nofault(addr, &insn, LOONGARCH_INSN_SIZE);
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raw_spin_unlock_irqrestore(&patch_lock, flags);
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return ret;
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}
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int larch_insn_patch_text(void *addr, u32 insn)
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{
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int ret;
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u32 *tp = addr;
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if ((unsigned long)tp & 3)
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return -EINVAL;
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ret = larch_insn_write(tp, insn);
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if (!ret)
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flush_icache_range((unsigned long)tp,
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(unsigned long)tp + LOONGARCH_INSN_SIZE);
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return ret;
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}
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u32 larch_insn_gen_nop(void)
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{
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return INSN_NOP;
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}
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u32 larch_insn_gen_b(unsigned long pc, unsigned long dest)
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{
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long offset = dest - pc;
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union loongarch_instruction insn;
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if ((offset & 3) || offset < -SZ_128M || offset >= SZ_128M) {
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pr_warn("The generated b instruction is out of range.\n");
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return INSN_BREAK;
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}
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emit_b(&insn, offset >> 2);
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return insn.word;
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}
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u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest)
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{
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long offset = dest - pc;
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union loongarch_instruction insn;
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if ((offset & 3) || offset < -SZ_128M || offset >= SZ_128M) {
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pr_warn("The generated bl instruction is out of range.\n");
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return INSN_BREAK;
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}
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emit_bl(&insn, offset >> 2);
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return insn.word;
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}
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u32 larch_insn_gen_break(int imm)
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{
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union loongarch_instruction insn;
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if (imm < 0 || imm >= SZ_32K) {
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pr_warn("The generated break instruction is out of range.\n");
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return INSN_BREAK;
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}
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emit_break(&insn, imm);
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return insn.word;
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}
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u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk)
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{
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union loongarch_instruction insn;
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emit_or(&insn, rd, rj, rk);
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return insn.word;
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}
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u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj)
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{
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return larch_insn_gen_or(rd, rj, 0);
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}
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u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm)
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{
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union loongarch_instruction insn;
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if (imm < -SZ_512K || imm >= SZ_512K) {
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pr_warn("The generated lu12i.w instruction is out of range.\n");
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return INSN_BREAK;
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}
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emit_lu12iw(&insn, rd, imm);
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return insn.word;
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}
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u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm)
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{
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union loongarch_instruction insn;
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if (imm < -SZ_512K || imm >= SZ_512K) {
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pr_warn("The generated lu32i.d instruction is out of range.\n");
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return INSN_BREAK;
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}
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emit_lu32id(&insn, rd, imm);
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return insn.word;
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}
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u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
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{
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union loongarch_instruction insn;
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if (imm < -SZ_2K || imm >= SZ_2K) {
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pr_warn("The generated lu52i.d instruction is out of range.\n");
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return INSN_BREAK;
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}
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emit_lu52id(&insn, rd, rj, imm);
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return insn.word;
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}
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u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
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{
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union loongarch_instruction insn;
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if ((imm & 3) || imm < -SZ_128K || imm >= SZ_128K) {
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pr_warn("The generated jirl instruction is out of range.\n");
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return INSN_BREAK;
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}
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emit_jirl(&insn, rd, rj, imm >> 2);
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return insn.word;
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}
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