mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
75ded18a5e
Add LSX and LASX implementations of xor operations, operating on 64 bytes (one L1 cache line) at a time, for a balance between memory utilization and instruction mix. Huacai confirmed that all future LoongArch implementations by Loongson (that we care) will likely also feature 64-byte cache lines, and experiments show no throughput improvement with further unrolling. Performance numbers measured during system boot on a 3A5000 @ 2.5GHz: > 8regs : 12702 MB/sec > 8regs_prefetch : 10920 MB/sec > 32regs : 12686 MB/sec > 32regs_prefetch : 10918 MB/sec > lsx : 17589 MB/sec > lasx : 26116 MB/sec Acked-by: Song Liu <song@kernel.org> Signed-off-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
68 lines
1.6 KiB
C
68 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
/*
|
|
* Copyright (C) 2023 WANG Xuerui <git@xen0n.name>
|
|
*/
|
|
#ifndef _ASM_LOONGARCH_XOR_H
|
|
#define _ASM_LOONGARCH_XOR_H
|
|
|
|
#include <asm/cpu-features.h>
|
|
#include <asm/xor_simd.h>
|
|
|
|
#ifdef CONFIG_CPU_HAS_LSX
|
|
static struct xor_block_template xor_block_lsx = {
|
|
.name = "lsx",
|
|
.do_2 = xor_lsx_2,
|
|
.do_3 = xor_lsx_3,
|
|
.do_4 = xor_lsx_4,
|
|
.do_5 = xor_lsx_5,
|
|
};
|
|
|
|
#define XOR_SPEED_LSX() \
|
|
do { \
|
|
if (cpu_has_lsx) \
|
|
xor_speed(&xor_block_lsx); \
|
|
} while (0)
|
|
#else /* CONFIG_CPU_HAS_LSX */
|
|
#define XOR_SPEED_LSX()
|
|
#endif /* CONFIG_CPU_HAS_LSX */
|
|
|
|
#ifdef CONFIG_CPU_HAS_LASX
|
|
static struct xor_block_template xor_block_lasx = {
|
|
.name = "lasx",
|
|
.do_2 = xor_lasx_2,
|
|
.do_3 = xor_lasx_3,
|
|
.do_4 = xor_lasx_4,
|
|
.do_5 = xor_lasx_5,
|
|
};
|
|
|
|
#define XOR_SPEED_LASX() \
|
|
do { \
|
|
if (cpu_has_lasx) \
|
|
xor_speed(&xor_block_lasx); \
|
|
} while (0)
|
|
#else /* CONFIG_CPU_HAS_LASX */
|
|
#define XOR_SPEED_LASX()
|
|
#endif /* CONFIG_CPU_HAS_LASX */
|
|
|
|
/*
|
|
* For grins, also test the generic routines.
|
|
*
|
|
* More importantly: it cannot be ruled out at this point of time, that some
|
|
* future (maybe reduced) models could run the vector algorithms slower than
|
|
* the scalar ones, maybe for errata or micro-op reasons. It may be
|
|
* appropriate to revisit this after one or two more uarch generations.
|
|
*/
|
|
#include <asm-generic/xor.h>
|
|
|
|
#undef XOR_TRY_TEMPLATES
|
|
#define XOR_TRY_TEMPLATES \
|
|
do { \
|
|
xor_speed(&xor_block_8regs); \
|
|
xor_speed(&xor_block_8regs_p); \
|
|
xor_speed(&xor_block_32regs); \
|
|
xor_speed(&xor_block_32regs_p); \
|
|
XOR_SPEED_LSX(); \
|
|
XOR_SPEED_LASX(); \
|
|
} while (0)
|
|
|
|
#endif /* _ASM_LOONGARCH_XOR_H */
|