mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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672999cfae
Inspired by commit 2e77a62cb3a6("arm64: extable: add a dedicated uaccess
handler"), do similar to LoongArch to add a dedicated uaccess exception
handler to update registers in exception context and subsequently return
back into the function which faulted, so we remove the need for fixups
specialized to each faulting instruction.
Add gpr-num.h here because we need to map the same GPR names to integer
constants, so that we can use this to build meta-data for the exception
fixups.
The compiler treats gpr 0 as zero rather than $r0, so set it separately
to .L__gpr_num_zero, otherwise the following assembly error will occurs:
{standard input}: Assembler messages:
{standard input}:1074: Error: invalid operands (*UND* and *ABS* sections) for `<<'
{standard input}:1160: Error: invalid operands (*UND* and *ABS* sections) for `<<'
make[1]: *** [scripts/Makefile.build:249: fs/fcntl.o] Error 1
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
94 lines
2.1 KiB
C
94 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_FUTEX_H
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#define _ASM_FUTEX_H
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/asm-extable.h>
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#include <asm/barrier.h>
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#include <asm/errno.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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{ \
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__asm__ __volatile__( \
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"1: ll.w %1, %4 # __futex_atomic_op\n" \
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" " insn " \n" \
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"2: sc.w $t0, %2 \n" \
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" beqz $t0, 1b \n" \
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"3: \n" \
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_ASM_EXTABLE_UACCESS_ERR(1b, 3b, %0) \
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_ASM_EXTABLE_UACCESS_ERR(2b, 3b, %0) \
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: "=r" (ret), "=&r" (oldval), \
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"=ZC" (*uaddr) \
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: "0" (0), "ZC" (*uaddr), "Jr" (oparg) \
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: "memory", "t0"); \
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}
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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int oldval = 0, ret = 0;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("move $t0, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add.w $t0, %1, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("or $t0, %1, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and $t0, %1, %z5", ret, oldval, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("xor $t0, %1, %z5", ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval)
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{
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int ret = 0;
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u32 val = 0;
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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__asm__ __volatile__(
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"# futex_atomic_cmpxchg_inatomic \n"
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"1: ll.w %1, %3 \n"
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" bne %1, %z4, 3f \n"
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" move $t0, %z5 \n"
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"2: sc.w $t0, %2 \n"
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" beqz $t0, 1b \n"
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"3: \n"
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__WEAK_LLSC_MB
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_ASM_EXTABLE_UACCESS_ERR(1b, 3b, %0)
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_ASM_EXTABLE_UACCESS_ERR(2b, 3b, %0)
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: "+r" (ret), "=&r" (val), "=ZC" (*uaddr)
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: "ZC" (*uaddr), "Jr" (oldval), "Jr" (newval)
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: "memory", "t0");
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*uval = val;
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return ret;
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}
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#endif /* _ASM_FUTEX_H */
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