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34e3c4500c
Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel resilience to different core implementations. BTW, IOCSR register definition appears to be a platform-specific spec instead of an architecture spec, even for the Loongson CPUs there is no guarantee that IOCSR will always present. Thus it's dangerous to perform IOCSR probing without checking CPU type and instruction availability. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
72 lines
2.8 KiB
C
72 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#ifndef __ASM_CPU_FEATURES_H
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#define __ASM_CPU_FEATURES_H
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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#define cpu_opt(opt) (cpu_data[0].options & (opt))
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#define cpu_has(feat) (cpu_data[0].options & BIT_ULL(feat))
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#define cpu_has_loongarch (cpu_has_loongarch32 | cpu_has_loongarch64)
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#define cpu_has_loongarch32 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_32BIT)
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#define cpu_has_loongarch64 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT)
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#ifdef CONFIG_32BIT
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# define cpu_has_64bits (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT)
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# define cpu_vabits 31
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# define cpu_pabits 31
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#endif
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#ifdef CONFIG_64BIT
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# define cpu_has_64bits 1
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# define cpu_vabits cpu_data[0].vabits
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# define cpu_pabits cpu_data[0].pabits
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# define __NEED_ADDRBITS_PROBE
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#endif
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/*
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* SMP assumption: Options of CPU 0 are a superset of all processors.
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* This is true for all known LoongArch systems.
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*/
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#define cpu_has_cpucfg cpu_opt(LOONGARCH_CPU_CPUCFG)
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#define cpu_has_lam cpu_opt(LOONGARCH_CPU_LAM)
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#define cpu_has_ual cpu_opt(LOONGARCH_CPU_UAL)
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#define cpu_has_fpu cpu_opt(LOONGARCH_CPU_FPU)
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#define cpu_has_lsx cpu_opt(LOONGARCH_CPU_LSX)
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#define cpu_has_lasx cpu_opt(LOONGARCH_CPU_LASX)
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#define cpu_has_crc32 cpu_opt(LOONGARCH_CPU_CRC32)
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#define cpu_has_complex cpu_opt(LOONGARCH_CPU_COMPLEX)
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#define cpu_has_crypto cpu_opt(LOONGARCH_CPU_CRYPTO)
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#define cpu_has_lvz cpu_opt(LOONGARCH_CPU_LVZ)
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#define cpu_has_lbt_x86 cpu_opt(LOONGARCH_CPU_LBT_X86)
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#define cpu_has_lbt_arm cpu_opt(LOONGARCH_CPU_LBT_ARM)
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#define cpu_has_lbt_mips cpu_opt(LOONGARCH_CPU_LBT_MIPS)
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#define cpu_has_lbt (cpu_has_lbt_x86|cpu_has_lbt_arm|cpu_has_lbt_mips)
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#define cpu_has_csr cpu_opt(LOONGARCH_CPU_CSR)
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#define cpu_has_iocsr cpu_opt(LOONGARCH_CPU_IOCSR)
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#define cpu_has_tlb cpu_opt(LOONGARCH_CPU_TLB)
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#define cpu_has_watch cpu_opt(LOONGARCH_CPU_WATCH)
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#define cpu_has_vint cpu_opt(LOONGARCH_CPU_VINT)
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#define cpu_has_csripi cpu_opt(LOONGARCH_CPU_CSRIPI)
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#define cpu_has_extioi cpu_opt(LOONGARCH_CPU_EXTIOI)
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#define cpu_has_prefetch cpu_opt(LOONGARCH_CPU_PREFETCH)
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#define cpu_has_pmp cpu_opt(LOONGARCH_CPU_PMP)
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#define cpu_has_perf cpu_opt(LOONGARCH_CPU_PMP)
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#define cpu_has_scalefreq cpu_opt(LOONGARCH_CPU_SCALEFREQ)
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#define cpu_has_flatmode cpu_opt(LOONGARCH_CPU_FLATMODE)
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#define cpu_has_eiodecode cpu_opt(LOONGARCH_CPU_EIODECODE)
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#define cpu_has_guestid cpu_opt(LOONGARCH_CPU_GUESTID)
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#define cpu_has_hypervisor cpu_opt(LOONGARCH_CPU_HYPERVISOR)
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#define cpu_has_ptw cpu_opt(LOONGARCH_CPU_PTW)
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#define cpu_has_lspw cpu_opt(LOONGARCH_CPU_LSPW)
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#define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT)
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#endif /* __ASM_CPU_FEATURES_H */
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