mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
6fb44438a5
Perf and PMU updates:
- Add support for new (v3) Hisilicon SLLC and DDRC PMUs
- Add support for Arm-NI PMU integrations that share interrupts between
clock domains within a given instance
- Allow SPE to be configured with a lower sample period than the
minimum recommendation advertised by PMSIDR_EL1.Interval
- Add suppport for Arm's "Branch Record Buffer Extension" (BRBE)
- Adjust the perf watchdog period according to cpu frequency changes
- Minor driver fixes and cleanups
Hardware features:
- Support for MTE store-only checking (FEAT_MTE_STORE_ONLY)
- Support for reporting the non-address bits during a synchronous MTE
tag check fault (FEAT_MTE_TAGGED_FAR)
- Optimise the TLBI when folding/unfolding contiguous PTEs on hardware
with FEAT_BBM (break-before-make) level 2 and no TLB conflict aborts
Software features:
- Enable HAVE_LIVEPATCH after implementing arch_stack_walk_reliable()
and using the text-poke API for late module relocations
- Force VMAP_STACK always on and change arm64_efi_rt_init() to use
arch_alloc_vmap_stack() in order to avoid KASAN false positives
ACPI:
- Improve SPCR handling and messaging on systems lacking an SPCR table
Debug:
- Simplify the debug exception entry path
- Drop redundant DBG_MDSCR_* macros
Kselftests:
- Cleanups and improvements for SME, SVE and FPSIMD tests
Miscellaneous:
- Optimise loop to reduce redundant operations in contpte_ptep_get()
- Remove ISB when resetting POR_EL0 during signal handling
- Mark the kernel as tainted on SEA and SError panic
- Remove redundant gcs_free() call
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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Catalin Marinas:
"A quick summary: perf support for Branch Record Buffer Extensions
(BRBE), typical PMU hardware updates, small additions to MTE for
store-only tag checking and exposing non-address bits to signal
handlers, HAVE_LIVEPATCH enabled on arm64, VMAP_STACK forced on.
There is also a TLBI optimisation on hardware that does not require
break-before-make when changing the user PTEs between contiguous and
non-contiguous.
More details:
Perf and PMU updates:
- Add support for new (v3) Hisilicon SLLC and DDRC PMUs
- Add support for Arm-NI PMU integrations that share interrupts
between clock domains within a given instance
- Allow SPE to be configured with a lower sample period than the
minimum recommendation advertised by PMSIDR_EL1.Interval
- Add suppport for Arm's "Branch Record Buffer Extension" (BRBE)
- Adjust the perf watchdog period according to cpu frequency changes
- Minor driver fixes and cleanups
Hardware features:
- Support for MTE store-only checking (FEAT_MTE_STORE_ONLY)
- Support for reporting the non-address bits during a synchronous MTE
tag check fault (FEAT_MTE_TAGGED_FAR)
- Optimise the TLBI when folding/unfolding contiguous PTEs on
hardware with FEAT_BBM (break-before-make) level 2 and no TLB
conflict aborts
Software features:
- Enable HAVE_LIVEPATCH after implementing arch_stack_walk_reliable()
and using the text-poke API for late module relocations
- Force VMAP_STACK always on and change arm64_efi_rt_init() to use
arch_alloc_vmap_stack() in order to avoid KASAN false positives
ACPI:
- Improve SPCR handling and messaging on systems lacking an SPCR
table
Debug:
- Simplify the debug exception entry path
- Drop redundant DBG_MDSCR_* macros
Kselftests:
- Cleanups and improvements for SME, SVE and FPSIMD tests
Miscellaneous:
- Optimise loop to reduce redundant operations in contpte_ptep_get()
- Remove ISB when resetting POR_EL0 during signal handling
- Mark the kernel as tainted on SEA and SError panic
- Remove redundant gcs_free() call"
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (93 commits)
arm64/gcs: task_gcs_el0_enable() should use passed task
arm64: Kconfig: Keep selects somewhat alphabetically ordered
arm64: signal: Remove ISB when resetting POR_EL0
kselftest/arm64: Handle attempts to disable SM on SME only systems
kselftest/arm64: Fix SVE write data generation for SME only systems
kselftest/arm64: Test SME on SME only systems in fp-ptrace
kselftest/arm64: Test FPSIMD format data writes via NT_ARM_SVE in fp-ptrace
kselftest/arm64: Allow sve-ptrace to run on SME only systems
arm64/mm: Drop redundant addr increment in set_huge_pte_at()
kselftest/arm4: Provide local defines for AT_HWCAP3
arm64: Mark kernel as tainted on SAE and SError panic
arm64/gcs: Don't call gcs_free() when releasing task_struct
drivers/perf: hisi: Support PMUs with no interrupt
drivers/perf: hisi: Relax the event number check of v2 PMUs
drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver
drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU information
drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver
drivers/perf: hisi: Simplify the probe process for each DDRC version
perf/arm-ni: Support sharing IRQs within an NI instance
perf/arm-ni: Consolidate CPU affinity handling
...
539 lines
13 KiB
ArmAsm
539 lines
13 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/mm/proc.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/pgtable.h>
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#include <linux/cfi_types.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/asm_pointer_auth.h>
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#include <asm/hwcap.h>
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#include <asm/kernel-pgtable.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/cpufeature.h>
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#include <asm/alternative.h>
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#include <asm/smp.h>
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#include <asm/sysreg.h>
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#ifdef CONFIG_ARM64_64K_PAGES
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#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
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#elif defined(CONFIG_ARM64_16K_PAGES)
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#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
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#else /* CONFIG_ARM64_4K_PAGES */
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#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
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#endif
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#ifdef CONFIG_RANDOMIZE_BASE
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#define TCR_KASLR_FLAGS TCR_NFD1
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#else
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#define TCR_KASLR_FLAGS 0
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#endif
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/* PTWs cacheable, inner/outer WBWA */
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#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
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#ifdef CONFIG_KASAN_SW_TAGS
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#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
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#else
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#define TCR_KASAN_SW_FLAGS 0
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#endif
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#ifdef CONFIG_KASAN_HW_TAGS
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#define TCR_MTE_FLAGS TCR_TCMA1 | TCR_TBI1 | TCR_TBID1
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#elif defined(CONFIG_ARM64_MTE)
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/*
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* The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
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* TBI being enabled at EL1.
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*/
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#define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
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#else
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#define TCR_MTE_FLAGS 0
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#endif
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/*
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* Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
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* changed during mte_cpu_setup to Normal Tagged if the system supports MTE.
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*/
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#define MAIR_EL1_SET \
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(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \
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MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \
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MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \
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MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \
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MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
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#ifdef CONFIG_CPU_PM
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/**
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* cpu_do_suspend - save CPU registers context
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*
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* x0: virtual address of context pointer
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*
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* This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
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*/
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SYM_FUNC_START(cpu_do_suspend)
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mrs x2, tpidr_el0
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mrs x3, tpidrro_el0
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mrs x4, contextidr_el1
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mrs x5, osdlr_el1
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mrs x6, cpacr_el1
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mrs x7, tcr_el1
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mrs x8, vbar_el1
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mrs x9, mdscr_el1
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mrs x10, oslsr_el1
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mrs x11, sctlr_el1
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get_this_cpu_offset x12
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mrs x13, sp_el0
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stp x2, x3, [x0]
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stp x4, x5, [x0, #16]
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stp x6, x7, [x0, #32]
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stp x8, x9, [x0, #48]
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stp x10, x11, [x0, #64]
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stp x12, x13, [x0, #80]
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/*
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* Save x18 as it may be used as a platform register, e.g. by shadow
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* call stack.
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*/
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str x18, [x0, #96]
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ret
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SYM_FUNC_END(cpu_do_suspend)
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/**
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* cpu_do_resume - restore CPU register context
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*
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* x0: Address of context pointer
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*/
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SYM_FUNC_START(cpu_do_resume)
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ldp x2, x3, [x0]
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ldp x4, x5, [x0, #16]
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ldp x6, x8, [x0, #32]
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ldp x9, x10, [x0, #48]
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ldp x11, x12, [x0, #64]
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ldp x13, x14, [x0, #80]
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/*
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* Restore x18, as it may be used as a platform register, and clear
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* the buffer to minimize the risk of exposure when used for shadow
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* call stack.
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*/
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ldr x18, [x0, #96]
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str xzr, [x0, #96]
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msr tpidr_el0, x2
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msr tpidrro_el0, x3
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msr contextidr_el1, x4
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msr cpacr_el1, x6
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/* Don't change t0sz here, mask those bits when restoring */
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mrs x7, tcr_el1
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bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
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msr tcr_el1, x8
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msr vbar_el1, x9
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msr mdscr_el1, x10
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msr sctlr_el1, x12
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set_this_cpu_offset x13
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msr sp_el0, x14
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/*
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* Restore oslsr_el1 by writing oslar_el1
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*/
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msr osdlr_el1, x5
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ubfx x11, x11, #1, #1
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msr oslar_el1, x11
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reset_pmuserenr_el0 x0 // Disable PMU access from EL0
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reset_amuserenr_el0 x0 // Disable AMU access from EL0
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alternative_if ARM64_HAS_RAS_EXTN
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msr_s SYS_DISR_EL1, xzr
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alternative_else_nop_endif
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ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
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isb
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ret
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SYM_FUNC_END(cpu_do_resume)
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#endif
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.pushsection ".idmap.text", "a"
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.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
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adrp \tmp1, reserved_pg_dir
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phys_to_ttbr \tmp2, \tmp1
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offset_ttbr1 \tmp2, \tmp1
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msr ttbr1_el1, \tmp2
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isb
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tlbi vmalle1
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dsb nsh
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isb
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.endm
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/*
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* void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
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*
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* This is the low-level counterpart to cpu_replace_ttbr1, and should not be
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* called by anything else. It can only be executed from a TTBR0 mapping.
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*/
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SYM_TYPED_FUNC_START(idmap_cpu_replace_ttbr1)
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__idmap_cpu_set_reserved_ttbr1 x1, x3
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offset_ttbr1 x0, x3
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msr ttbr1_el1, x0
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isb
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ret
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SYM_FUNC_END(idmap_cpu_replace_ttbr1)
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SYM_FUNC_ALIAS(__pi_idmap_cpu_replace_ttbr1, idmap_cpu_replace_ttbr1)
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.popsection
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#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
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#define KPTI_NG_PTE_FLAGS (PTE_ATTRINDX(MT_NORMAL) | PTE_TYPE_PAGE | \
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PTE_AF | PTE_SHARED | PTE_UXN | PTE_WRITE)
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.pushsection ".idmap.text", "a"
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.macro pte_to_phys, phys, pte
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and \phys, \pte, #PTE_ADDR_LOW
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#ifdef CONFIG_ARM64_PA_BITS_52
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and \pte, \pte, #PTE_ADDR_HIGH
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orr \phys, \phys, \pte, lsl #PTE_ADDR_HIGH_SHIFT
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#endif
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.endm
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.macro kpti_mk_tbl_ng, type, num_entries
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add end_\type\()p, cur_\type\()p, #\num_entries * 8
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.Ldo_\type:
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ldr \type, [cur_\type\()p], #8 // Load the entry and advance
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tbz \type, #0, .Lnext_\type // Skip invalid and
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tbnz \type, #11, .Lnext_\type // non-global entries
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orr \type, \type, #PTE_NG // Same bit for blocks and pages
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str \type, [cur_\type\()p, #-8] // Update the entry
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.ifnc \type, pte
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tbnz \type, #1, .Lderef_\type
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.endif
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.Lnext_\type:
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cmp cur_\type\()p, end_\type\()p
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b.ne .Ldo_\type
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.endm
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/*
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* Dereference the current table entry and map it into the temporary
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* fixmap slot associated with the current level.
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*/
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.macro kpti_map_pgtbl, type, level
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str xzr, [temp_pte, #8 * (\level + 2)] // break before make
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dsb nshst
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add pte, temp_pte, #PAGE_SIZE * (\level + 2)
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lsr pte, pte, #12
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tlbi vaae1, pte
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dsb nsh
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isb
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phys_to_pte pte, cur_\type\()p
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add cur_\type\()p, temp_pte, #PAGE_SIZE * (\level + 2)
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orr pte, pte, pte_flags
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str pte, [temp_pte, #8 * (\level + 2)]
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dsb nshst
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.endm
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/*
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* void __kpti_install_ng_mappings(int cpu, int num_secondaries, phys_addr_t temp_pgd,
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* unsigned long temp_pte_va)
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*
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* Called exactly once from stop_machine context by each CPU found during boot.
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*/
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.pushsection ".data", "aw", %progbits
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SYM_DATA(__idmap_kpti_flag, .long 1)
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.popsection
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SYM_TYPED_FUNC_START(idmap_kpti_install_ng_mappings)
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cpu .req w0
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temp_pte .req x0
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num_cpus .req w1
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pte_flags .req x1
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temp_pgd_phys .req x2
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swapper_ttb .req x3
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flag_ptr .req x4
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cur_pgdp .req x5
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end_pgdp .req x6
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pgd .req x7
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cur_pudp .req x8
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end_pudp .req x9
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cur_pmdp .req x11
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end_pmdp .req x12
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cur_ptep .req x14
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end_ptep .req x15
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pte .req x16
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valid .req x17
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cur_p4dp .req x19
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end_p4dp .req x20
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mov x5, x3 // preserve temp_pte arg
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mrs swapper_ttb, ttbr1_el1
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adr_l flag_ptr, __idmap_kpti_flag
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cbnz cpu, __idmap_kpti_secondary
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#if CONFIG_PGTABLE_LEVELS > 4
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stp x29, x30, [sp, #-32]!
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mov x29, sp
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stp x19, x20, [sp, #16]
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#endif
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/* We're the boot CPU. Wait for the others to catch up */
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sevl
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1: wfe
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ldaxr w17, [flag_ptr]
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eor w17, w17, num_cpus
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cbnz w17, 1b
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/* Switch to the temporary page tables on this CPU only */
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__idmap_cpu_set_reserved_ttbr1 x8, x9
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offset_ttbr1 temp_pgd_phys, x8
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msr ttbr1_el1, temp_pgd_phys
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isb
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mov temp_pte, x5
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mov_q pte_flags, KPTI_NG_PTE_FLAGS
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/* Everybody is enjoying the idmap, so we can rewrite swapper. */
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#ifdef CONFIG_ARM64_LPA2
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/*
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* If LPA2 support is configured, but 52-bit virtual addressing is not
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* enabled at runtime, we will fall back to one level of paging less,
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* and so we have to walk swapper_pg_dir as if we dereferenced its
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* address from a PGD level entry, and terminate the PGD level loop
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* right after.
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*/
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adrp pgd, swapper_pg_dir // walk &swapper_pg_dir at the next level
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mov cur_pgdp, end_pgdp // must be equal to terminate the PGD loop
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alternative_if_not ARM64_HAS_VA52
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b .Lderef_pgd // skip to the next level
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alternative_else_nop_endif
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/*
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* LPA2 based 52-bit virtual addressing requires 52-bit physical
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* addressing to be enabled as well. In this case, the shareability
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* bits are repurposed as physical address bits, and should not be
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* set in pte_flags.
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*/
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bic pte_flags, pte_flags, #PTE_SHARED
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#endif
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/* PGD */
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adrp cur_pgdp, swapper_pg_dir
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kpti_map_pgtbl pgd, -1
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kpti_mk_tbl_ng pgd, PTRS_PER_PGD
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/* Ensure all the updated entries are visible to secondary CPUs */
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dsb ishst
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/* We're done: fire up swapper_pg_dir again */
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__idmap_cpu_set_reserved_ttbr1 x8, x9
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msr ttbr1_el1, swapper_ttb
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isb
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/* Set the flag to zero to indicate that we're all done */
|
|
str wzr, [flag_ptr]
|
|
#if CONFIG_PGTABLE_LEVELS > 4
|
|
ldp x19, x20, [sp, #16]
|
|
ldp x29, x30, [sp], #32
|
|
#endif
|
|
ret
|
|
|
|
.Lderef_pgd:
|
|
/* P4D */
|
|
.if CONFIG_PGTABLE_LEVELS > 4
|
|
p4d .req x30
|
|
pte_to_phys cur_p4dp, pgd
|
|
kpti_map_pgtbl p4d, 0
|
|
kpti_mk_tbl_ng p4d, PTRS_PER_P4D
|
|
b .Lnext_pgd
|
|
.else /* CONFIG_PGTABLE_LEVELS <= 4 */
|
|
p4d .req pgd
|
|
.set .Lnext_p4d, .Lnext_pgd
|
|
.endif
|
|
|
|
.Lderef_p4d:
|
|
/* PUD */
|
|
.if CONFIG_PGTABLE_LEVELS > 3
|
|
pud .req x10
|
|
pte_to_phys cur_pudp, p4d
|
|
kpti_map_pgtbl pud, 1
|
|
kpti_mk_tbl_ng pud, PTRS_PER_PUD
|
|
b .Lnext_p4d
|
|
.else /* CONFIG_PGTABLE_LEVELS <= 3 */
|
|
pud .req pgd
|
|
.set .Lnext_pud, .Lnext_pgd
|
|
.endif
|
|
|
|
.Lderef_pud:
|
|
/* PMD */
|
|
.if CONFIG_PGTABLE_LEVELS > 2
|
|
pmd .req x13
|
|
pte_to_phys cur_pmdp, pud
|
|
kpti_map_pgtbl pmd, 2
|
|
kpti_mk_tbl_ng pmd, PTRS_PER_PMD
|
|
b .Lnext_pud
|
|
.else /* CONFIG_PGTABLE_LEVELS <= 2 */
|
|
pmd .req pgd
|
|
.set .Lnext_pmd, .Lnext_pgd
|
|
.endif
|
|
|
|
.Lderef_pmd:
|
|
/* PTE */
|
|
pte_to_phys cur_ptep, pmd
|
|
kpti_map_pgtbl pte, 3
|
|
kpti_mk_tbl_ng pte, PTRS_PER_PTE
|
|
b .Lnext_pmd
|
|
|
|
.unreq cpu
|
|
.unreq temp_pte
|
|
.unreq num_cpus
|
|
.unreq pte_flags
|
|
.unreq temp_pgd_phys
|
|
.unreq cur_pgdp
|
|
.unreq end_pgdp
|
|
.unreq pgd
|
|
.unreq cur_pudp
|
|
.unreq end_pudp
|
|
.unreq pud
|
|
.unreq cur_pmdp
|
|
.unreq end_pmdp
|
|
.unreq pmd
|
|
.unreq cur_ptep
|
|
.unreq end_ptep
|
|
.unreq pte
|
|
.unreq valid
|
|
.unreq cur_p4dp
|
|
.unreq end_p4dp
|
|
.unreq p4d
|
|
|
|
/* Secondary CPUs end up here */
|
|
__idmap_kpti_secondary:
|
|
/* Uninstall swapper before surgery begins */
|
|
__idmap_cpu_set_reserved_ttbr1 x16, x17
|
|
|
|
/* Increment the flag to let the boot CPU we're ready */
|
|
1: ldxr w16, [flag_ptr]
|
|
add w16, w16, #1
|
|
stxr w17, w16, [flag_ptr]
|
|
cbnz w17, 1b
|
|
|
|
/* Wait for the boot CPU to finish messing around with swapper */
|
|
sevl
|
|
1: wfe
|
|
ldxr w16, [flag_ptr]
|
|
cbnz w16, 1b
|
|
|
|
/* All done, act like nothing happened */
|
|
msr ttbr1_el1, swapper_ttb
|
|
isb
|
|
ret
|
|
|
|
.unreq swapper_ttb
|
|
.unreq flag_ptr
|
|
SYM_FUNC_END(idmap_kpti_install_ng_mappings)
|
|
.popsection
|
|
#endif
|
|
|
|
/*
|
|
* __cpu_setup
|
|
*
|
|
* Initialise the processor for turning the MMU on.
|
|
*
|
|
* Output:
|
|
* Return in x0 the value of the SCTLR_EL1 register.
|
|
*/
|
|
.pushsection ".idmap.text", "a"
|
|
SYM_FUNC_START(__cpu_setup)
|
|
tlbi vmalle1 // Invalidate local TLB
|
|
dsb nsh
|
|
|
|
msr cpacr_el1, xzr // Reset cpacr_el1
|
|
mov x1, MDSCR_EL1_TDCC // Reset mdscr_el1 and disable
|
|
msr mdscr_el1, x1 // access to the DCC from EL0
|
|
reset_pmuserenr_el0 x1 // Disable PMU access from EL0
|
|
reset_amuserenr_el0 x1 // Disable AMU access from EL0
|
|
|
|
/*
|
|
* Default values for VMSA control registers. These will be adjusted
|
|
* below depending on detected CPU features.
|
|
*/
|
|
mair .req x17
|
|
tcr .req x16
|
|
tcr2 .req x15
|
|
mov_q mair, MAIR_EL1_SET
|
|
mov_q tcr, TCR_T0SZ(IDMAP_VA_BITS) | TCR_T1SZ(VA_BITS_MIN) | TCR_CACHE_FLAGS | \
|
|
TCR_SHARED | TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
|
|
TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
|
|
mov tcr2, xzr
|
|
|
|
tcr_clear_errata_bits tcr, x9, x5
|
|
|
|
#ifdef CONFIG_ARM64_VA_BITS_52
|
|
mov x9, #64 - VA_BITS
|
|
alternative_if ARM64_HAS_VA52
|
|
tcr_set_t1sz tcr, x9
|
|
#ifdef CONFIG_ARM64_LPA2
|
|
orr tcr, tcr, #TCR_DS
|
|
#endif
|
|
alternative_else_nop_endif
|
|
#endif
|
|
|
|
/*
|
|
* Set the IPS bits in TCR_EL1.
|
|
*/
|
|
tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
|
|
#ifdef CONFIG_ARM64_HW_AFDBM
|
|
/*
|
|
* Enable hardware update of the Access Flags bit.
|
|
* Hardware dirty bit management is enabled later,
|
|
* via capabilities.
|
|
*/
|
|
mrs x9, ID_AA64MMFR1_EL1
|
|
ubfx x9, x9, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, #4
|
|
cbz x9, 1f
|
|
orr tcr, tcr, #TCR_HA // hardware Access flag update
|
|
#ifdef CONFIG_ARM64_HAFT
|
|
cmp x9, ID_AA64MMFR1_EL1_HAFDBS_HAFT
|
|
b.lt 1f
|
|
orr tcr2, tcr2, TCR2_EL1_HAFT
|
|
#endif /* CONFIG_ARM64_HAFT */
|
|
1:
|
|
#endif /* CONFIG_ARM64_HW_AFDBM */
|
|
msr mair_el1, mair
|
|
msr tcr_el1, tcr
|
|
|
|
mrs_s x1, SYS_ID_AA64MMFR3_EL1
|
|
ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
|
|
cbz x1, .Lskip_indirection
|
|
|
|
mov_q x0, PIE_E0_ASM
|
|
msr REG_PIRE0_EL1, x0
|
|
mov_q x0, PIE_E1_ASM
|
|
msr REG_PIR_EL1, x0
|
|
|
|
orr tcr2, tcr2, TCR2_EL1_PIE
|
|
|
|
.Lskip_indirection:
|
|
|
|
mrs_s x1, SYS_ID_AA64MMFR3_EL1
|
|
ubfx x1, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, #4
|
|
cbz x1, 1f
|
|
msr REG_TCR2_EL1, tcr2
|
|
1:
|
|
|
|
/*
|
|
* Prepare SCTLR
|
|
*/
|
|
mov_q x0, INIT_SCTLR_EL1_MMU_ON
|
|
ret // return to head.S
|
|
|
|
.unreq mair
|
|
.unreq tcr
|
|
.unreq tcr2
|
|
SYM_FUNC_END(__cpu_setup)
|