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Address bytes shifted with a single 64 bit page table entry (any page table level) has been always hard coded as 3 (aka 2^3 = 8). Although intuitive it is not very readable or easy to reason about. Besides it is going to change with D128, where each 128 bit page table entry will shift address bytes by 4 (aka 2^4 = 16) instead. Let's just formalise this address bytes shift value into a new macro called PTDESC_ORDER establishing a logical abstraction, thus improving readability as well. While here re-organize EARLY_LEVEL macro along with its dependents for better clarity. This does not cause any functional change. Also replace all (PAGE_SHIFT - PTDESC_ORDER) instances with PTDESC_TABLE_SHIFT. Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Andrey Ryabinin <ryabinin.a.a@gmail.com> Cc: Alexander Potapenko <glider@google.com> Cc: Andrey Konovalov <andreyknvl@gmail.com> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Ryan Roberts <ryan.roberts@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: kasan-dev@googlegroups.com Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Ryan Roberts <ryan.roberts@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20250311045710.550625-1-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
412 lines
12 KiB
C
412 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* This file contains kasan initialization code for ARM64.
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Author: Andrey Ryabinin <ryabinin.a.a@gmail.com>
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*/
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#define pr_fmt(fmt) "kasan: " fmt
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#include <linux/kasan.h>
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#include <linux/kernel.h>
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#include <linux/sched/task.h>
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#include <linux/memblock.h>
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#include <linux/start_kernel.h>
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#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/kernel-pgtable.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/sections.h>
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#include <asm/tlbflush.h>
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#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
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static pgd_t tmp_pg_dir[PTRS_PER_PTE] __initdata __aligned(PAGE_SIZE);
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/*
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* The p*d_populate functions call virt_to_phys implicitly so they can't be used
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* directly on kernel symbols (bm_p*d). All the early functions are called too
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* early to use lm_alias so __p*d_populate functions must be used to populate
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* with the physical address from __pa_symbol.
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*/
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static phys_addr_t __init kasan_alloc_zeroed_page(int node)
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{
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void *p = memblock_alloc_try_nid(PAGE_SIZE, PAGE_SIZE,
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__pa(MAX_DMA_ADDRESS),
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MEMBLOCK_ALLOC_NOLEAKTRACE, node);
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if (!p)
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panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%llx\n",
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__func__, PAGE_SIZE, PAGE_SIZE, node,
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__pa(MAX_DMA_ADDRESS));
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return __pa(p);
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}
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static phys_addr_t __init kasan_alloc_raw_page(int node)
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{
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void *p = memblock_alloc_try_nid_raw(PAGE_SIZE, PAGE_SIZE,
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__pa(MAX_DMA_ADDRESS),
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MEMBLOCK_ALLOC_NOLEAKTRACE,
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node);
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if (!p)
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panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%llx\n",
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__func__, PAGE_SIZE, PAGE_SIZE, node,
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__pa(MAX_DMA_ADDRESS));
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return __pa(p);
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}
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static pte_t *__init kasan_pte_offset(pmd_t *pmdp, unsigned long addr, int node,
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bool early)
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{
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if (pmd_none(READ_ONCE(*pmdp))) {
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phys_addr_t pte_phys = early ?
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__pa_symbol(kasan_early_shadow_pte)
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: kasan_alloc_zeroed_page(node);
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__pmd_populate(pmdp, pte_phys, PMD_TYPE_TABLE);
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}
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return early ? pte_offset_kimg(pmdp, addr)
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: pte_offset_kernel(pmdp, addr);
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}
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static pmd_t *__init kasan_pmd_offset(pud_t *pudp, unsigned long addr, int node,
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bool early)
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{
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if (pud_none(READ_ONCE(*pudp))) {
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phys_addr_t pmd_phys = early ?
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__pa_symbol(kasan_early_shadow_pmd)
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: kasan_alloc_zeroed_page(node);
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__pud_populate(pudp, pmd_phys, PUD_TYPE_TABLE);
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}
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return early ? pmd_offset_kimg(pudp, addr) : pmd_offset(pudp, addr);
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}
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static pud_t *__init kasan_pud_offset(p4d_t *p4dp, unsigned long addr, int node,
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bool early)
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{
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if (p4d_none(READ_ONCE(*p4dp))) {
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phys_addr_t pud_phys = early ?
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__pa_symbol(kasan_early_shadow_pud)
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: kasan_alloc_zeroed_page(node);
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__p4d_populate(p4dp, pud_phys, P4D_TYPE_TABLE);
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}
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return early ? pud_offset_kimg(p4dp, addr) : pud_offset(p4dp, addr);
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}
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static p4d_t *__init kasan_p4d_offset(pgd_t *pgdp, unsigned long addr, int node,
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bool early)
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{
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if (pgd_none(READ_ONCE(*pgdp))) {
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phys_addr_t p4d_phys = early ?
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__pa_symbol(kasan_early_shadow_p4d)
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: kasan_alloc_zeroed_page(node);
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__pgd_populate(pgdp, p4d_phys, PGD_TYPE_TABLE);
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}
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return early ? p4d_offset_kimg(pgdp, addr) : p4d_offset(pgdp, addr);
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}
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static void __init kasan_pte_populate(pmd_t *pmdp, unsigned long addr,
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unsigned long end, int node, bool early)
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{
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unsigned long next;
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pte_t *ptep = kasan_pte_offset(pmdp, addr, node, early);
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do {
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phys_addr_t page_phys = early ?
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__pa_symbol(kasan_early_shadow_page)
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: kasan_alloc_raw_page(node);
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if (!early)
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memset(__va(page_phys), KASAN_SHADOW_INIT, PAGE_SIZE);
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next = addr + PAGE_SIZE;
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__set_pte(ptep, pfn_pte(__phys_to_pfn(page_phys), PAGE_KERNEL));
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} while (ptep++, addr = next, addr != end && pte_none(__ptep_get(ptep)));
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}
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static void __init kasan_pmd_populate(pud_t *pudp, unsigned long addr,
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unsigned long end, int node, bool early)
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{
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unsigned long next;
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pmd_t *pmdp = kasan_pmd_offset(pudp, addr, node, early);
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do {
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next = pmd_addr_end(addr, end);
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kasan_pte_populate(pmdp, addr, next, node, early);
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} while (pmdp++, addr = next, addr != end && pmd_none(READ_ONCE(*pmdp)));
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}
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static void __init kasan_pud_populate(p4d_t *p4dp, unsigned long addr,
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unsigned long end, int node, bool early)
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{
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unsigned long next;
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pud_t *pudp = kasan_pud_offset(p4dp, addr, node, early);
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do {
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next = pud_addr_end(addr, end);
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kasan_pmd_populate(pudp, addr, next, node, early);
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} while (pudp++, addr = next, addr != end && pud_none(READ_ONCE(*pudp)));
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}
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static void __init kasan_p4d_populate(pgd_t *pgdp, unsigned long addr,
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unsigned long end, int node, bool early)
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{
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unsigned long next;
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p4d_t *p4dp = kasan_p4d_offset(pgdp, addr, node, early);
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do {
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next = p4d_addr_end(addr, end);
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kasan_pud_populate(p4dp, addr, next, node, early);
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} while (p4dp++, addr = next, addr != end && p4d_none(READ_ONCE(*p4dp)));
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}
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static void __init kasan_pgd_populate(unsigned long addr, unsigned long end,
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int node, bool early)
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{
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unsigned long next;
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pgd_t *pgdp;
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pgdp = pgd_offset_k(addr);
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do {
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next = pgd_addr_end(addr, end);
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kasan_p4d_populate(pgdp, addr, next, node, early);
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} while (pgdp++, addr = next, addr != end);
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}
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#if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS > 4
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#define SHADOW_ALIGN P4D_SIZE
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#else
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#define SHADOW_ALIGN PUD_SIZE
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#endif
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/*
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* Return whether 'addr' is aligned to the size covered by a root level
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* descriptor.
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*/
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static bool __init root_level_aligned(u64 addr)
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{
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int shift = (ARM64_HW_PGTABLE_LEVELS(vabits_actual) - 1) * PTDESC_TABLE_SHIFT;
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return (addr % (PAGE_SIZE << shift)) == 0;
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}
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/* The early shadow maps everything to a single page of zeroes */
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asmlinkage void __init kasan_early_init(void)
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{
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BUILD_BUG_ON(KASAN_SHADOW_OFFSET !=
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KASAN_SHADOW_END - (1UL << (64 - KASAN_SHADOW_SCALE_SHIFT)));
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BUILD_BUG_ON(!IS_ALIGNED(_KASAN_SHADOW_START(VA_BITS), SHADOW_ALIGN));
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BUILD_BUG_ON(!IS_ALIGNED(_KASAN_SHADOW_START(VA_BITS_MIN), SHADOW_ALIGN));
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BUILD_BUG_ON(!IS_ALIGNED(KASAN_SHADOW_END, SHADOW_ALIGN));
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if (!root_level_aligned(KASAN_SHADOW_START)) {
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/*
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* The start address is misaligned, and so the next level table
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* will be shared with the linear region. This can happen with
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* 4 or 5 level paging, so install a generic pte_t[] as the
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* next level. This prevents the kasan_pgd_populate call below
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* from inserting an entry that refers to the shared KASAN zero
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* shadow pud_t[]/p4d_t[], which could end up getting corrupted
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* when the linear region is mapped.
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*/
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static pte_t tbl[PTRS_PER_PTE] __page_aligned_bss;
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pgd_t *pgdp = pgd_offset_k(KASAN_SHADOW_START);
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set_pgd(pgdp, __pgd(__pa_symbol(tbl) | PGD_TYPE_TABLE));
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}
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kasan_pgd_populate(KASAN_SHADOW_START, KASAN_SHADOW_END, NUMA_NO_NODE,
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true);
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}
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/* Set up full kasan mappings, ensuring that the mapped pages are zeroed */
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static void __init kasan_map_populate(unsigned long start, unsigned long end,
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int node)
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{
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kasan_pgd_populate(start & PAGE_MASK, PAGE_ALIGN(end), node, false);
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}
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/*
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* Return the descriptor index of 'addr' in the root level table
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*/
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static int __init root_level_idx(u64 addr)
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{
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/*
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* On 64k pages, the TTBR1 range root tables are extended for 52-bit
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* virtual addressing, and TTBR1 will simply point to the pgd_t entry
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* that covers the start of the 48-bit addressable VA space if LVA is
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* not implemented. This means we need to index the table as usual,
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* instead of masking off bits based on vabits_actual.
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*/
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u64 vabits = IS_ENABLED(CONFIG_ARM64_64K_PAGES) ? VA_BITS
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: vabits_actual;
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int shift = (ARM64_HW_PGTABLE_LEVELS(vabits) - 1) * PTDESC_TABLE_SHIFT;
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return (addr & ~_PAGE_OFFSET(vabits)) >> (shift + PAGE_SHIFT);
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}
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/*
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* Clone a next level table from swapper_pg_dir into tmp_pg_dir
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*/
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static void __init clone_next_level(u64 addr, pgd_t *tmp_pg_dir, pud_t *pud)
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{
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int idx = root_level_idx(addr);
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pgd_t pgd = READ_ONCE(swapper_pg_dir[idx]);
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pud_t *pudp = (pud_t *)__phys_to_kimg(__pgd_to_phys(pgd));
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memcpy(pud, pudp, PAGE_SIZE);
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tmp_pg_dir[idx] = __pgd(__phys_to_pgd_val(__pa_symbol(pud)) |
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PUD_TYPE_TABLE);
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}
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/*
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* Return the descriptor index of 'addr' in the next level table
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*/
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static int __init next_level_idx(u64 addr)
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{
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int shift = (ARM64_HW_PGTABLE_LEVELS(vabits_actual) - 2) * PTDESC_TABLE_SHIFT;
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return (addr >> (shift + PAGE_SHIFT)) % PTRS_PER_PTE;
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}
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/*
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* Dereference the table descriptor at 'pgd_idx' and clear the entries from
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* 'start' to 'end' (exclusive) from the table.
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*/
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static void __init clear_next_level(int pgd_idx, int start, int end)
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{
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pgd_t pgd = READ_ONCE(swapper_pg_dir[pgd_idx]);
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pud_t *pudp = (pud_t *)__phys_to_kimg(__pgd_to_phys(pgd));
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memset(&pudp[start], 0, (end - start) * sizeof(pud_t));
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}
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static void __init clear_shadow(u64 start, u64 end)
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{
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int l = root_level_idx(start), m = root_level_idx(end);
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if (!root_level_aligned(start))
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clear_next_level(l++, next_level_idx(start), PTRS_PER_PTE);
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if (!root_level_aligned(end))
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clear_next_level(m, 0, next_level_idx(end));
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memset(&swapper_pg_dir[l], 0, (m - l) * sizeof(pgd_t));
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}
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static void __init kasan_init_shadow(void)
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{
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static pud_t pud[2][PTRS_PER_PUD] __initdata __aligned(PAGE_SIZE);
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u64 kimg_shadow_start, kimg_shadow_end;
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u64 mod_shadow_start;
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u64 vmalloc_shadow_end;
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phys_addr_t pa_start, pa_end;
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u64 i;
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kimg_shadow_start = (u64)kasan_mem_to_shadow(KERNEL_START) & PAGE_MASK;
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kimg_shadow_end = PAGE_ALIGN((u64)kasan_mem_to_shadow(KERNEL_END));
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mod_shadow_start = (u64)kasan_mem_to_shadow((void *)MODULES_VADDR);
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vmalloc_shadow_end = (u64)kasan_mem_to_shadow((void *)VMALLOC_END);
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/*
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* We are going to perform proper setup of shadow memory.
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* At first we should unmap early shadow (clear_pgds() call below).
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* However, instrumented code couldn't execute without shadow memory.
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* tmp_pg_dir used to keep early shadow mapped until full shadow
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* setup will be finished.
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*/
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memcpy(tmp_pg_dir, swapper_pg_dir, sizeof(tmp_pg_dir));
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/*
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* If the start or end address of the shadow region is not aligned to
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* the root level size, we have to allocate a temporary next-level table
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* in each case, clone the next level of descriptors, and install the
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* table into tmp_pg_dir. Note that with 5 levels of paging, the next
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* level will in fact be p4d_t, but that makes no difference in this
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* case.
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*/
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if (!root_level_aligned(KASAN_SHADOW_START))
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clone_next_level(KASAN_SHADOW_START, tmp_pg_dir, pud[0]);
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if (!root_level_aligned(KASAN_SHADOW_END))
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clone_next_level(KASAN_SHADOW_END, tmp_pg_dir, pud[1]);
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dsb(ishst);
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cpu_replace_ttbr1(lm_alias(tmp_pg_dir));
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clear_shadow(KASAN_SHADOW_START, KASAN_SHADOW_END);
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kasan_map_populate(kimg_shadow_start, kimg_shadow_end,
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early_pfn_to_nid(virt_to_pfn(lm_alias(KERNEL_START))));
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kasan_populate_early_shadow(kasan_mem_to_shadow((void *)PAGE_END),
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(void *)mod_shadow_start);
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BUILD_BUG_ON(VMALLOC_START != MODULES_END);
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kasan_populate_early_shadow((void *)vmalloc_shadow_end,
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(void *)KASAN_SHADOW_END);
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for_each_mem_range(i, &pa_start, &pa_end) {
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void *start = (void *)__phys_to_virt(pa_start);
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void *end = (void *)__phys_to_virt(pa_end);
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if (start >= end)
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break;
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kasan_map_populate((unsigned long)kasan_mem_to_shadow(start),
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(unsigned long)kasan_mem_to_shadow(end),
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early_pfn_to_nid(virt_to_pfn(start)));
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}
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/*
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* KAsan may reuse the contents of kasan_early_shadow_pte directly,
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* so we should make sure that it maps the zero page read-only.
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*/
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for (i = 0; i < PTRS_PER_PTE; i++)
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__set_pte(&kasan_early_shadow_pte[i],
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pfn_pte(sym_to_pfn(kasan_early_shadow_page),
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PAGE_KERNEL_RO));
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memset(kasan_early_shadow_page, KASAN_SHADOW_INIT, PAGE_SIZE);
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cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
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}
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static void __init kasan_init_depth(void)
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{
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init_task.kasan_depth = 0;
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}
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#ifdef CONFIG_KASAN_VMALLOC
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void __init kasan_populate_early_vm_area_shadow(void *start, unsigned long size)
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{
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unsigned long shadow_start, shadow_end;
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if (!is_vmalloc_or_module_addr(start))
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return;
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shadow_start = (unsigned long)kasan_mem_to_shadow(start);
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shadow_start = ALIGN_DOWN(shadow_start, PAGE_SIZE);
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shadow_end = (unsigned long)kasan_mem_to_shadow(start + size);
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shadow_end = ALIGN(shadow_end, PAGE_SIZE);
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kasan_map_populate(shadow_start, shadow_end, NUMA_NO_NODE);
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}
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#endif
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void __init kasan_init(void)
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{
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kasan_init_shadow();
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kasan_init_depth();
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#if defined(CONFIG_KASAN_GENERIC)
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/*
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* Generic KASAN is now fully initialized.
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* Software and Hardware Tag-Based modes still require
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* kasan_init_sw_tags() and kasan_init_hw_tags() correspondingly.
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*/
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pr_info("KernelAddressSanitizer initialized (generic)\n");
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#endif
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}
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#endif /* CONFIG_KASAN_GENERIC || CONFIG_KASAN_SW_TAGS */
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