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8af3e8ab09
In order to avoid further embarassing bugs, enforce that the GICv3 sysreg table is actually sorted, just like all the other tables. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Link: https://lore.kernel.org/r/20250718111154.104029-4-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
489 lines
12 KiB
C
489 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* VGIC system registers handling functions for AArch64 mode
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*/
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include "vgic/vgic.h"
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#include "sys_regs.h"
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static int set_gic_ctlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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u32 host_pri_bits, host_id_bits, host_seis, host_a3v, seis, a3v;
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struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu;
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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/*
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* Disallow restoring VM state if not supported by this
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* hardware.
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*/
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host_pri_bits = FIELD_GET(ICC_CTLR_EL1_PRI_BITS_MASK, val) + 1;
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if (host_pri_bits > vgic_v3_cpu->num_pri_bits)
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return -EINVAL;
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vgic_v3_cpu->num_pri_bits = host_pri_bits;
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host_id_bits = FIELD_GET(ICC_CTLR_EL1_ID_BITS_MASK, val);
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if (host_id_bits > vgic_v3_cpu->num_id_bits)
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return -EINVAL;
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vgic_v3_cpu->num_id_bits = host_id_bits;
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host_seis = FIELD_GET(ICH_VTR_EL2_SEIS, kvm_vgic_global_state.ich_vtr_el2);
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seis = FIELD_GET(ICC_CTLR_EL1_SEIS_MASK, val);
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if (host_seis != seis)
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return -EINVAL;
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host_a3v = FIELD_GET(ICH_VTR_EL2_A3V, kvm_vgic_global_state.ich_vtr_el2);
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a3v = FIELD_GET(ICC_CTLR_EL1_A3V_MASK, val);
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if (host_a3v != a3v)
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return -EINVAL;
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/*
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* Here set VMCR.CTLR in ICC_CTLR_EL1 layout.
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* The vgic_set_vmcr() will convert to ICH_VMCR layout.
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*/
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vmcr.cbpr = FIELD_GET(ICC_CTLR_EL1_CBPR_MASK, val);
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vmcr.eoim = FIELD_GET(ICC_CTLR_EL1_EOImode_MASK, val);
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vgic_set_vmcr(vcpu, &vmcr);
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return 0;
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}
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static int get_gic_ctlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *valp)
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{
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struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu;
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struct vgic_vmcr vmcr;
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u64 val;
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vgic_get_vmcr(vcpu, &vmcr);
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val = 0;
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val |= FIELD_PREP(ICC_CTLR_EL1_PRI_BITS_MASK, vgic_v3_cpu->num_pri_bits - 1);
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val |= FIELD_PREP(ICC_CTLR_EL1_ID_BITS_MASK, vgic_v3_cpu->num_id_bits);
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val |= FIELD_PREP(ICC_CTLR_EL1_SEIS_MASK,
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FIELD_GET(ICH_VTR_EL2_SEIS,
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kvm_vgic_global_state.ich_vtr_el2));
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val |= FIELD_PREP(ICC_CTLR_EL1_A3V_MASK,
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FIELD_GET(ICH_VTR_EL2_A3V, kvm_vgic_global_state.ich_vtr_el2));
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/*
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* The VMCR.CTLR value is in ICC_CTLR_EL1 layout.
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* Extract it directly using ICC_CTLR_EL1 reg definitions.
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*/
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val |= FIELD_PREP(ICC_CTLR_EL1_CBPR_MASK, vmcr.cbpr);
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val |= FIELD_PREP(ICC_CTLR_EL1_EOImode_MASK, vmcr.eoim);
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*valp = val;
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return 0;
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}
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static int set_gic_pmr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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vmcr.pmr = FIELD_GET(ICC_PMR_EL1_MASK, val);
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vgic_set_vmcr(vcpu, &vmcr);
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return 0;
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}
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static int get_gic_pmr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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*val = FIELD_PREP(ICC_PMR_EL1_MASK, vmcr.pmr);
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return 0;
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}
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static int set_gic_bpr0(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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vmcr.bpr = FIELD_GET(ICC_BPR0_EL1_MASK, val);
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vgic_set_vmcr(vcpu, &vmcr);
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return 0;
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}
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static int get_gic_bpr0(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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*val = FIELD_PREP(ICC_BPR0_EL1_MASK, vmcr.bpr);
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return 0;
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}
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static int set_gic_bpr1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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if (!vmcr.cbpr) {
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vmcr.abpr = FIELD_GET(ICC_BPR1_EL1_MASK, val);
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vgic_set_vmcr(vcpu, &vmcr);
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}
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return 0;
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}
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static int get_gic_bpr1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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if (!vmcr.cbpr)
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*val = FIELD_PREP(ICC_BPR1_EL1_MASK, vmcr.abpr);
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else
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*val = min((vmcr.bpr + 1), 7U);
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return 0;
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}
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static int set_gic_grpen0(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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vmcr.grpen0 = FIELD_GET(ICC_IGRPEN0_EL1_MASK, val);
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vgic_set_vmcr(vcpu, &vmcr);
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return 0;
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}
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static int get_gic_grpen0(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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*val = FIELD_PREP(ICC_IGRPEN0_EL1_MASK, vmcr.grpen0);
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return 0;
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}
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static int set_gic_grpen1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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vmcr.grpen1 = FIELD_GET(ICC_IGRPEN1_EL1_MASK, val);
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vgic_set_vmcr(vcpu, &vmcr);
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return 0;
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}
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static int get_gic_grpen1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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*val = FIELD_GET(ICC_IGRPEN1_EL1_MASK, vmcr.grpen1);
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return 0;
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}
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static void set_apr_reg(struct kvm_vcpu *vcpu, u64 val, u8 apr, u8 idx)
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{
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struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
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if (apr)
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vgicv3->vgic_ap1r[idx] = val;
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else
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vgicv3->vgic_ap0r[idx] = val;
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}
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static u64 get_apr_reg(struct kvm_vcpu *vcpu, u8 apr, u8 idx)
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{
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struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
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if (apr)
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return vgicv3->vgic_ap1r[idx];
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else
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return vgicv3->vgic_ap0r[idx];
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}
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static int set_gic_ap0r(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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u8 idx = r->Op2 & 3;
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if (idx > vgic_v3_max_apr_idx(vcpu))
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return -EINVAL;
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set_apr_reg(vcpu, val, 0, idx);
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return 0;
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}
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static int get_gic_ap0r(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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u8 idx = r->Op2 & 3;
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if (idx > vgic_v3_max_apr_idx(vcpu))
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return -EINVAL;
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*val = get_apr_reg(vcpu, 0, idx);
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return 0;
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}
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static int set_gic_ap1r(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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u8 idx = r->Op2 & 3;
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if (idx > vgic_v3_max_apr_idx(vcpu))
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return -EINVAL;
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set_apr_reg(vcpu, val, 1, idx);
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return 0;
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}
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static int get_gic_ap1r(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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u8 idx = r->Op2 & 3;
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if (idx > vgic_v3_max_apr_idx(vcpu))
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return -EINVAL;
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*val = get_apr_reg(vcpu, 1, idx);
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return 0;
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}
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static int set_gic_sre(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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/* Validate SRE bit */
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if (!(val & ICC_SRE_EL1_SRE))
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return -EINVAL;
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return 0;
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}
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static int get_gic_sre(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
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*val = vgicv3->vgic_sre;
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return 0;
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}
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static int set_gic_ich_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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__vcpu_assign_sys_reg(vcpu, r->reg, val);
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return 0;
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}
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static int get_gic_ich_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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*val = __vcpu_sys_reg(vcpu, r->reg);
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return 0;
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}
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static int set_gic_ich_apr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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u8 idx = r->Op2 & 3;
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if (idx > vgic_v3_max_apr_idx(vcpu))
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return -EINVAL;
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return set_gic_ich_reg(vcpu, r, val);
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}
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static int get_gic_ich_apr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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u8 idx = r->Op2 & 3;
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if (idx > vgic_v3_max_apr_idx(vcpu))
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return -EINVAL;
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return get_gic_ich_reg(vcpu, r, val);
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}
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static int set_gic_icc_sre(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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if (val != KVM_ICC_SRE_EL2)
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return -EINVAL;
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return 0;
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}
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static int get_gic_icc_sre(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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*val = KVM_ICC_SRE_EL2;
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return 0;
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}
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static int set_gic_ich_vtr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 val)
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{
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if (val != kvm_get_guest_vtr_el2())
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return -EINVAL;
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return 0;
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}
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static int get_gic_ich_vtr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
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u64 *val)
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{
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*val = kvm_get_guest_vtr_el2();
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return 0;
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}
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static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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{
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return vcpu_has_nv(vcpu) ? 0 : REG_HIDDEN;
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}
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#define __EL2_REG(r, acc, i) \
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{ \
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SYS_DESC(SYS_ ## r), \
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.get_user = get_gic_ ## acc, \
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.set_user = set_gic_ ## acc, \
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.reg = i, \
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.visibility = el2_visibility, \
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}
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#define EL2_REG(r, acc) __EL2_REG(r, acc, r)
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#define EL2_REG_RO(r, acc) __EL2_REG(r, acc, 0)
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static const struct sys_reg_desc gic_v3_icc_reg_descs[] = {
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{ SYS_DESC(SYS_ICC_PMR_EL1),
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.set_user = set_gic_pmr, .get_user = get_gic_pmr, },
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{ SYS_DESC(SYS_ICC_BPR0_EL1),
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.set_user = set_gic_bpr0, .get_user = get_gic_bpr0, },
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{ SYS_DESC(SYS_ICC_AP0R0_EL1),
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.set_user = set_gic_ap0r, .get_user = get_gic_ap0r, },
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{ SYS_DESC(SYS_ICC_AP0R1_EL1),
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.set_user = set_gic_ap0r, .get_user = get_gic_ap0r, },
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{ SYS_DESC(SYS_ICC_AP0R2_EL1),
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.set_user = set_gic_ap0r, .get_user = get_gic_ap0r, },
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{ SYS_DESC(SYS_ICC_AP0R3_EL1),
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.set_user = set_gic_ap0r, .get_user = get_gic_ap0r, },
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{ SYS_DESC(SYS_ICC_AP1R0_EL1),
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.set_user = set_gic_ap1r, .get_user = get_gic_ap1r, },
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{ SYS_DESC(SYS_ICC_AP1R1_EL1),
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.set_user = set_gic_ap1r, .get_user = get_gic_ap1r, },
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{ SYS_DESC(SYS_ICC_AP1R2_EL1),
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.set_user = set_gic_ap1r, .get_user = get_gic_ap1r, },
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{ SYS_DESC(SYS_ICC_AP1R3_EL1),
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.set_user = set_gic_ap1r, .get_user = get_gic_ap1r, },
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{ SYS_DESC(SYS_ICC_BPR1_EL1),
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.set_user = set_gic_bpr1, .get_user = get_gic_bpr1, },
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{ SYS_DESC(SYS_ICC_CTLR_EL1),
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.set_user = set_gic_ctlr, .get_user = get_gic_ctlr, },
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{ SYS_DESC(SYS_ICC_SRE_EL1),
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.set_user = set_gic_sre, .get_user = get_gic_sre, },
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{ SYS_DESC(SYS_ICC_IGRPEN0_EL1),
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.set_user = set_gic_grpen0, .get_user = get_gic_grpen0, },
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{ SYS_DESC(SYS_ICC_IGRPEN1_EL1),
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.set_user = set_gic_grpen1, .get_user = get_gic_grpen1, },
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EL2_REG(ICH_AP0R0_EL2, ich_apr),
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EL2_REG(ICH_AP0R1_EL2, ich_apr),
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EL2_REG(ICH_AP0R2_EL2, ich_apr),
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EL2_REG(ICH_AP0R3_EL2, ich_apr),
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EL2_REG(ICH_AP1R0_EL2, ich_apr),
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EL2_REG(ICH_AP1R1_EL2, ich_apr),
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EL2_REG(ICH_AP1R2_EL2, ich_apr),
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EL2_REG(ICH_AP1R3_EL2, ich_apr),
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EL2_REG_RO(ICC_SRE_EL2, icc_sre),
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EL2_REG(ICH_HCR_EL2, ich_reg),
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EL2_REG_RO(ICH_VTR_EL2, ich_vtr),
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EL2_REG(ICH_VMCR_EL2, ich_reg),
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EL2_REG(ICH_LR0_EL2, ich_reg),
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EL2_REG(ICH_LR1_EL2, ich_reg),
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EL2_REG(ICH_LR2_EL2, ich_reg),
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EL2_REG(ICH_LR3_EL2, ich_reg),
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EL2_REG(ICH_LR4_EL2, ich_reg),
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EL2_REG(ICH_LR5_EL2, ich_reg),
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EL2_REG(ICH_LR6_EL2, ich_reg),
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EL2_REG(ICH_LR7_EL2, ich_reg),
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EL2_REG(ICH_LR8_EL2, ich_reg),
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EL2_REG(ICH_LR9_EL2, ich_reg),
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EL2_REG(ICH_LR10_EL2, ich_reg),
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EL2_REG(ICH_LR11_EL2, ich_reg),
|
|
EL2_REG(ICH_LR12_EL2, ich_reg),
|
|
EL2_REG(ICH_LR13_EL2, ich_reg),
|
|
EL2_REG(ICH_LR14_EL2, ich_reg),
|
|
EL2_REG(ICH_LR15_EL2, ich_reg),
|
|
};
|
|
|
|
const struct sys_reg_desc *vgic_v3_get_sysreg_table(unsigned int *sz)
|
|
{
|
|
*sz = ARRAY_SIZE(gic_v3_icc_reg_descs);
|
|
return gic_v3_icc_reg_descs;
|
|
}
|
|
|
|
static u64 attr_to_id(u64 attr)
|
|
{
|
|
return ARM64_SYS_REG(FIELD_GET(KVM_REG_ARM_VGIC_SYSREG_OP0_MASK, attr),
|
|
FIELD_GET(KVM_REG_ARM_VGIC_SYSREG_OP1_MASK, attr),
|
|
FIELD_GET(KVM_REG_ARM_VGIC_SYSREG_CRN_MASK, attr),
|
|
FIELD_GET(KVM_REG_ARM_VGIC_SYSREG_CRM_MASK, attr),
|
|
FIELD_GET(KVM_REG_ARM_VGIC_SYSREG_OP2_MASK, attr));
|
|
}
|
|
|
|
int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
|
|
{
|
|
const struct sys_reg_desc *r;
|
|
|
|
r = get_reg_by_id(attr_to_id(attr->attr), gic_v3_icc_reg_descs,
|
|
ARRAY_SIZE(gic_v3_icc_reg_descs));
|
|
|
|
if (r && !sysreg_hidden(vcpu, r))
|
|
return 0;
|
|
|
|
return -ENXIO;
|
|
}
|
|
|
|
int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu,
|
|
struct kvm_device_attr *attr,
|
|
bool is_write)
|
|
{
|
|
struct kvm_one_reg reg = {
|
|
.id = attr_to_id(attr->attr),
|
|
.addr = attr->addr,
|
|
};
|
|
|
|
if (is_write)
|
|
return kvm_sys_reg_set_user(vcpu, ®, gic_v3_icc_reg_descs,
|
|
ARRAY_SIZE(gic_v3_icc_reg_descs));
|
|
else
|
|
return kvm_sys_reg_get_user(vcpu, ®, gic_v3_icc_reg_descs,
|
|
ARRAY_SIZE(gic_v3_icc_reg_descs));
|
|
}
|