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cbf218627d
Filesystems like resctrl use the cache-id exposed via sysfs to identify groups of CPUs. The value is also used for PCIe cache steering tags. On DT platforms cache-id is not something that is described in the device-tree, but instead generated from the smallest MPIDR of the CPUs associated with that cache. The cache-id exposed to user-space has historically been 32 bits. MPIDR values may be larger than 32 bits. MPIDR only has 32 bits worth of affinity data, but the aff3 field lives above 32bits. The corresponding lower bits are masked out by MPIDR_HWID_BITMASK and contain an SMT flag and Uni-Processor flag. Swizzzle the aff3 field into the bottom 32 bits and using that. In case more affinity fields are added in the future, the upper RES0 area should be checked. Returning a value greater than 32 bits from this helper will cause the caller to give up on allocating cache-ids. Signed-off-by: James Morse <james.morse@arm.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Link: https://lore.kernel.org/r/20250711182743.30141-4-james.morse@arm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
140 lines
3.8 KiB
C
140 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_CACHE_H
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#define __ASM_CACHE_H
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#define L1_CACHE_SHIFT (6)
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define CLIDR_LOUU_SHIFT 27
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#define CLIDR_LOC_SHIFT 24
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#define CLIDR_LOUIS_SHIFT 21
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#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
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#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
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#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
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/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
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#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
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#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
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#define CLIDR_CTYPE(clidr, level) \
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(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
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/* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */
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#define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT)
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/*
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* Memory returned by kmalloc() may be used for DMA, so we must make
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* sure that all such allocations are cache aligned. Otherwise,
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* unrelated code may cause parts of the buffer to be read into the
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* cache before the transfer is done, causing old data to be seen by
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* the CPU.
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*/
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#define ARCH_DMA_MINALIGN (128)
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#define ARCH_KMALLOC_MINALIGN (8)
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#if !defined(__ASSEMBLY__) && !defined(BUILD_VDSO)
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#include <linux/bitops.h>
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#include <linux/kasan-enabled.h>
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#include <asm/cputype.h>
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#include <asm/mte-def.h>
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#include <asm/sysreg.h>
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#ifdef CONFIG_KASAN_SW_TAGS
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#define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
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#elif defined(CONFIG_KASAN_HW_TAGS)
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static inline unsigned int arch_slab_minalign(void)
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{
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return kasan_hw_tags_enabled() ? MTE_GRANULE_SIZE :
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__alignof__(unsigned long long);
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}
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#define arch_slab_minalign() arch_slab_minalign()
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#endif
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#define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
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#define ICACHEF_ALIASING 0
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extern unsigned long __icache_flags;
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/*
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* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
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* permitted in the I-cache.
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*/
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static inline int icache_is_aliasing(void)
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{
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return test_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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static inline u32 cache_type_cwg(void)
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{
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return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());
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}
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#define __read_mostly __section(".data..read_mostly")
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static inline int cache_line_size_of_cpu(void)
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{
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u32 cwg = cache_type_cwg();
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return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
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}
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int cache_line_size(void);
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#define dma_get_cache_alignment cache_line_size
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/* Compress a u64 MPIDR value into 32 bits. */
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static inline u64 arch_compact_of_hwid(u64 id)
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{
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u64 aff3 = MPIDR_AFFINITY_LEVEL(id, 3);
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/*
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* These bits are expected to be RES0. If not, return a value with
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* the upper 32 bits set to force the caller to give up on 32 bit
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* cache ids.
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*/
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if (FIELD_GET(GENMASK_ULL(63, 40), id))
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return id;
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return (aff3 << 24) | FIELD_GET(GENMASK_ULL(23, 0), id);
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}
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#define arch_compact_of_hwid arch_compact_of_hwid
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/*
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* Read the effective value of CTR_EL0.
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*
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* According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
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* section D10.2.33 "CTR_EL0, Cache Type Register" :
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*
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* CTR_EL0.IDC reports the data cache clean requirements for
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* instruction to data coherence.
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*
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* 0 - dcache clean to PoU is required unless :
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* (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
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* 1 - dcache clean to PoU is not required for i-to-d coherence.
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*
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* This routine provides the CTR_EL0 with the IDC field updated to the
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* effective state.
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*/
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static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
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{
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u32 ctr = read_cpuid_cachetype();
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if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {
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u64 clidr = read_sysreg(clidr_el1);
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if (CLIDR_LOC(clidr) == 0 ||
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(CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
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ctr |= BIT(CTR_EL0_IDC_SHIFT);
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}
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return ctr;
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}
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#endif /* !defined(__ASSEMBLY__) && !defined(BUILD_VDSO) */
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#endif
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