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The PMU appears to have a separate register for filtering 'guest' exception levels (i.e. EL1 and !ELIsInHost(EL0)) which has the same layout as PMCR1_EL1. Conveniently, there exists a VHE register alias (PMCR1_EL12) that can be used to configure it. Support guest events by programming the EL12 register with the intended guest kernel/userspace filters. Limit support for guest events to VHE (i.e. kernel running at EL2), as it avoids involving KVM to context switch PMU registers. VHE is the only supported mode on M* parts anyway, so this isn't an actual feature limitation. Tested-by: Janne Grunau <j@jannau.net> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250305202641.428114-3-oliver.upton@linux.dev Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
65 lines
2.3 KiB
C
65 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef __ASM_APPLE_M1_PMU_h
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#define __ASM_APPLE_M1_PMU_h
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#include <linux/bits.h>
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#include <asm/sysreg.h>
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/* Counters */
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#define SYS_IMP_APL_PMC0_EL1 sys_reg(3, 2, 15, 0, 0)
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#define SYS_IMP_APL_PMC1_EL1 sys_reg(3, 2, 15, 1, 0)
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#define SYS_IMP_APL_PMC2_EL1 sys_reg(3, 2, 15, 2, 0)
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#define SYS_IMP_APL_PMC3_EL1 sys_reg(3, 2, 15, 3, 0)
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#define SYS_IMP_APL_PMC4_EL1 sys_reg(3, 2, 15, 4, 0)
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#define SYS_IMP_APL_PMC5_EL1 sys_reg(3, 2, 15, 5, 0)
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#define SYS_IMP_APL_PMC6_EL1 sys_reg(3, 2, 15, 6, 0)
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#define SYS_IMP_APL_PMC7_EL1 sys_reg(3, 2, 15, 7, 0)
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#define SYS_IMP_APL_PMC8_EL1 sys_reg(3, 2, 15, 9, 0)
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#define SYS_IMP_APL_PMC9_EL1 sys_reg(3, 2, 15, 10, 0)
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/* Core PMC control register */
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#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0)
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#define PMCR0_CNT_ENABLE_0_7 GENMASK(7, 0)
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#define PMCR0_IMODE GENMASK(10, 8)
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#define PMCR0_IMODE_OFF 0
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#define PMCR0_IMODE_PMI 1
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#define PMCR0_IMODE_AIC 2
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#define PMCR0_IMODE_HALT 3
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#define PMCR0_IMODE_FIQ 4
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#define PMCR0_IACT BIT(11)
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#define PMCR0_PMI_ENABLE_0_7 GENMASK(19, 12)
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#define PMCR0_STOP_CNT_ON_PMI BIT(20)
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#define PMCR0_CNT_GLOB_L2C_EVT BIT(21)
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#define PMCR0_DEFER_PMI_TO_ERET BIT(22)
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#define PMCR0_ALLOW_CNT_EN_EL0 BIT(30)
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#define PMCR0_CNT_ENABLE_8_9 GENMASK(33, 32)
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#define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44)
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#define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0)
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#define SYS_IMP_APL_PMCR1_EL12 sys_reg(3, 1, 15, 7, 2)
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#define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8)
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#define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16)
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#define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40)
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#define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48)
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#define SYS_IMP_APL_PMCR2_EL1 sys_reg(3, 1, 15, 2, 0)
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#define SYS_IMP_APL_PMCR3_EL1 sys_reg(3, 1, 15, 3, 0)
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#define SYS_IMP_APL_PMCR4_EL1 sys_reg(3, 1, 15, 4, 0)
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#define SYS_IMP_APL_PMESR0_EL1 sys_reg(3, 1, 15, 5, 0)
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#define PMESR0_EVT_CNT_2 GENMASK(7, 0)
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#define PMESR0_EVT_CNT_3 GENMASK(15, 8)
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#define PMESR0_EVT_CNT_4 GENMASK(23, 16)
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#define PMESR0_EVT_CNT_5 GENMASK(31, 24)
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#define SYS_IMP_APL_PMESR1_EL1 sys_reg(3, 1, 15, 6, 0)
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#define PMESR1_EVT_CNT_6 GENMASK(7, 0)
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#define PMESR1_EVT_CNT_7 GENMASK(15, 8)
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#define PMESR1_EVT_CNT_8 GENMASK(23, 16)
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#define PMESR1_EVT_CNT_9 GENMASK(31, 24)
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#define SYS_IMP_APL_PMSR_EL1 sys_reg(3, 1, 15, 13, 0)
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#define PMSR_OVERFLOW GENMASK(9, 0)
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#endif /* __ASM_APPLE_M1_PMU_h */
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