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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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399f14ff66
bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas R-Car SoCs. All SoC require CPG clock and its input clock, RST Reset, PFC pin control and PRR ID register access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains these IP. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250209180616.160253-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
410 lines
7.1 KiB
Text
410 lines
7.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the common parts shared by the White Hawk CPU and
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* White Hawk Single boards
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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aliases {
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ethernet0 = &avb0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &hscif0;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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stdout-path = "serial0:921600n8";
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};
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sn65dsi86_refclk: clk-x6 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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};
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keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&keys_pins>;
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pinctrl-names = "default";
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key-1 {
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gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_1>;
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label = "SW47";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-2 {
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gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_2>;
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label = "SW48";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-3 {
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gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_3>;
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label = "SW49";
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wakeup-source;
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debounce-interval = <20>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led-1 {
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gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <1>;
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};
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led-2 {
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gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <2>;
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};
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led-3 {
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gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <3>;
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};
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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memory@480000000 {
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device_type = "memory";
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reg = <0x4 0x80000000 0x0 0x80000000>;
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};
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memory@600000000 {
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device_type = "memory";
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reg = <0x6 0x00000000 0x1 0x00000000>;
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};
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mini-dp-con {
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compatible = "dp-connector";
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label = "CN5";
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type = "mini";
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port {
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mini_dp_con_in: endpoint {
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remote-endpoint = <&sn65dsi86_out>;
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};
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};
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};
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pcie_clk: clk-9fgv0841-pci {
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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#clock-cells = <0>;
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};
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reg_1p2v: regulator-1p2v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.2V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&avb0 {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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phy-handle = <&avb0_phy>;
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tx-internal-delay-ps = <2000>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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avb0_phy: ethernet-phy@0 {
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&dsi0 {
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status = "okay";
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ports {
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port@1 {
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dsi0_out: endpoint {
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remote-endpoint = <&sn65dsi86_in>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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&du {
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status = "okay";
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&hscif0 {
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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bootph-all;
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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io_expander_a: gpio@20 {
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compatible = "onnn,pca9654";
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reg = <0x20>;
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interrupts-extended = <&gpio0 0 IRQ_TYPE_LEVEL_LOW>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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eeprom@50 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "cpu-board";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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bridge@2c {
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pinctrl-0 = <&irq0_pins>;
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pinctrl-names = "default";
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compatible = "ti,sn65dsi86";
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reg = <0x2c>;
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clocks = <&sn65dsi86_refclk>;
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clock-names = "refclk";
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interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
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enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
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vccio-supply = <®_1p8v>;
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vpll-supply = <®_1p8v>;
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vcca-supply = <®_1p2v>;
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vcc-supply = <®_1p2v>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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sn65dsi86_in: endpoint {
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remote-endpoint = <&dsi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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sn65dsi86_out: endpoint {
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remote-endpoint = <&mini_dp_con_in>;
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};
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};
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};
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};
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};
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&mmc0 {
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pinctrl-0 = <&mmc_pins>;
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pinctrl-1 = <&mmc_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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bus-width = <8>;
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no-sd;
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no-sdio;
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non-removable;
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full-pwr-cycle-in-suspend;
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status = "okay";
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};
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&pcie0_clkref {
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compatible = "gpio-gate-clock";
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clocks = <&pcie_clk>;
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enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
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/delete-property/ clock-frequency;
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};
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&pciec0 {
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reset-gpios = <&io_expander_a 0 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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avb0_pins: avb0 {
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mux {
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groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
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"avb0_txcrefclk";
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function = "avb0";
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};
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pins_mdio {
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groups = "avb0_mdio";
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drive-strength = <21>;
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};
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pins_mii {
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groups = "avb0_rgmii";
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drive-strength = <21>;
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};
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};
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hscif0_pins: hscif0 {
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groups = "hscif0_data";
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function = "hscif0";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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i2c1_pins: i2c1 {
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groups = "i2c1";
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function = "i2c1";
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};
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irq0_pins: irq0 {
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groups = "intc_ex_irq0_a";
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function = "intc_ex";
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};
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keys_pins: keys {
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pins = "GP_5_0", "GP_5_1", "GP_5_2";
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bias-pull-up;
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};
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mmc_pins: mmc {
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groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
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function = "mmc";
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power-source = <1800>;
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};
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qspi0_pins: qspi0 {
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groups = "qspi0_ctrl", "qspi0_data4";
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function = "qspi0";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk";
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function = "scif_clk";
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};
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};
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&rpc {
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pinctrl-0 = <&qspi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "spansion,s25fs512s", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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spi-rx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot@0 {
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reg = <0x0 0x1200000>;
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read-only;
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};
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user@1200000 {
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reg = <0x1200000 0x2e00000>;
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};
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};
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};
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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};
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&scif_clk {
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clock-frequency = <24000000>;
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};
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