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cc018b98a9
Add a DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through the PMOD1_3A interface available on the Renesas RZ SMARC Carrier II board. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250120130936.1080069-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
40 lines
962 B
C
40 lines
962 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II
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* boards.
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#ifndef __RZG3S_SMARC_SWITCHES_H__
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#define __RZG3S_SMARC_SWITCHES_H__
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/*
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* On-board switches' states:
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* @SW_OFF: switch's state is OFF
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* @SW_ON: switch's state is ON
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*/
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#define SW_OFF 0
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#define SW_ON 1
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/*
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* SW_CONFIG[x] switches' states:
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* @SW_CONFIG2:
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* SW_OFF - SD0 is connected to eMMC
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* SW_ON - SD0 is connected to uSD0 card
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* @SW_CONFIG3:
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* SW_OFF - SD2 is connected to SoC
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* SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
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*/
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#define SW_CONFIG2 SW_OFF
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#define SW_CONFIG3 SW_ON
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/*
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* SW_OPT_MUX[x] switches' states:
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* @SW_OPT_MUX4:
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* SW_OFF - The SMARC SER0 signals are routed to M.2 Key E UART
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* SW_ON - The SMARC SER0 signals are routed to PMOD1
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*/
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#define SW_OPT_MUX4 SW_ON
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#endif /* __RZG3S_SMARC_SWITCHES_H__ */
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