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The GPT4 IOs are available on the carrier board's PMOD0 connector (J1). Enable the GPT on the carrier board by adding the GPT pinmux and node on the carrier board dtsi file. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424054050.28310-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
45 lines
1.2 KiB
Text
45 lines
1.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/V2L SMARC EVK board
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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/dts-v1/;
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/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
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#define PMOD1_SER0 1
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/*
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* To enable MTU3a PWM on PMOD0,
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* Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
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* enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
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*/
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#define PMOD_MTU3 0
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#if (PMOD_MTU3 && PMOD1_SER0)
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#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
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#endif
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#define MTU3_COUNTER_Z_PHASE_SIGNAL 0
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#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
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#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
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#endif
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/*
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* To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the
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* PMOD0 connector (J1), enable PMOD0_GPT by setting "#define PMOD0_GPT 1"
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* below.
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*/
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#define PMOD0_GPT 0
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#include "r9a07g054l2.dtsi"
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#include "rzg2l-smarc-som.dtsi"
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#include "rzg2l-smarc-pinfunction.dtsi"
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#include "rz-smarc-common.dtsi"
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#include "rzg2l-smarc.dtsi"
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/ {
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model = "Renesas SMARC EVK based on r9a07g054l2";
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compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054";
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};
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