linux/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * IPQ9574 RDP board common device tree source
 *
 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "ipq9574.dtsi"

/ {
	aliases {
		serial0 = &blsp1_uart2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	regulator_fixed_3p3: s3300 {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
		regulator-name = "fixed_3p3";
	};

	regulator_fixed_0p925: s0925 {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <925000>;
		regulator-max-microvolt = <925000>;
		regulator-boot-on;
		regulator-always-on;
		regulator-name = "fixed_0p925";
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&gpio_keys_default>;
		pinctrl-names = "default";

		button-wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
			debounce-interval = <60>;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&gpio_leds_default>;
		pinctrl-names = "default";

		led-0 {
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_WLAN;
			gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "phy0tx";
			default-state = "off";
		};
	};
};

&blsp1_spi0 {
	pinctrl-0 = <&spi_0_pins>;
	pinctrl-names = "default";
	status = "okay";

	flash@0 {
		compatible = "micron,n25q128a11", "jedec,spi-nor";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
	};
};

&blsp1_uart2 {
	pinctrl-0 = <&uart2_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&rpm_requests {
	regulators {
		compatible = "qcom,rpm-mp5496-regulators";

		ipq9574_s1: s1 {
		/*
		 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
		 * During regulator registration, kernel not knowing the initial voltage,
		 * considers it as zero and brings up the regulators with minimum supported voltage.
		 * Update the regulator-min-microvolt with SVS voltage of 725mV so that
		 * the regulators are brought up with 725mV which is sufficient for all the
		 * corner parts to operate at 800MHz
		 */
			regulator-min-microvolt = <725000>;
			regulator-max-microvolt = <1075000>;
		};

		mp5496_l2: l2 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
			regulator-boot-on;
		};

		mp5496_l5: l5 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
			regulator-boot-on;
		};
	};
};

&sleep_clk {
	clock-frequency = <32000>;
};

&tlmm {
	spi_0_pins: spi-0-state {
		pins = "gpio11", "gpio12", "gpio13", "gpio14";
		function = "blsp0_spi";
		drive-strength = <8>;
		bias-disable;
	};

	gpio_keys_default: gpio-keys-default-state {
		pins = "gpio37";
		function = "gpio";
		drive-strength = <8>;
		bias-pull-up;
	};

	gpio_leds_default: gpio-leds-default-state {
		pins = "gpio64";
		function = "gpio";
		drive-strength = <8>;
		bias-pull-up;
	};

	qpic_snand_default_state: qpic-snand-default-state {
		clock-pins {
			pins = "gpio5";
			function = "qspi_clk";
			drive-strength = <8>;
			bias-disable;
		};

		cs-pins {
			pins = "gpio4";
			function = "qspi_cs";
			drive-strength = <8>;
			bias-disable;
		};

		data-pins {
			pins = "gpio0", "gpio1", "gpio2", "gpio3";
			function = "qspi_data";
			drive-strength = <8>;
			bias-disable;
		};
	};
};

&qpic_bam {
	status = "okay";
};

&qpic_nand {
	pinctrl-0 = <&qpic_snand_default_state>;
	pinctrl-names = "default";

	status = "okay";

	flash@0 {
		compatible = "spi-nand";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		nand-ecc-engine = <&qpic_nand>;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;
	};
};

&usb_0_dwc3 {
	dr_mode = "host";
};

&usb_0_qmpphy {
	vdda-pll-supply = <&mp5496_l5>;
	vdda-phy-supply = <&regulator_fixed_0p925>;

	status = "okay";
};

&usb_0_qusbphy {
	vdd-supply = <&regulator_fixed_0p925>;
	vdda-pll-supply = <&mp5496_l5>;
	vdda-phy-dpdm-supply = <&regulator_fixed_3p3>;

	status = "okay";
};

&usb3 {
	status = "okay";
};

/*
 * The bootstrap pins for the board select the XO clock frequency
 * (48 MHZ or 96 MHZ used for different RDP type board). This setting
 * automatically enables the right dividers, to ensure the reference
 * clock output from WiFi to the CMN PLL is 48 MHZ.
 */
&ref_48mhz_clk {
	clock-div = <1>;
	clock-mult = <1>;
};

/*
 * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
 * from WiFi output clock 48 MHZ divided by 2.
 */
&xo_board_clk {
	clock-div = <2>;
	clock-mult = <1>;
};

&xo_clk {
	clock-frequency = <48000000>;
};