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b0d011d484
Add the minimal dtsi support for i.MX943. i.MX943 is the first SoC of i.MX94 Family, create a common dtsi for the whole i.MX94 family, and the specific dtsi part for i.MX943. The clock, power domain and perf index need to be used by the device nodes for resource reference, add them along with the dtsi support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
148 lines
3.3 KiB
Text
148 lines
3.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2025 NXP
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*/
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#include "imx94.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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idle-states {
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entry-method = "psci";
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cpu_pd_wait: cpu-pd-wait {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010033>;
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local-timer-stop;
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entry-latency-us = <1000>;
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exit-latency-us = <700>;
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min-residency-us = <2700>;
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wakeup-latency-us = <1500>;
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x0>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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power-domains = <&scmi_perf IMX94_PERF_A55>;
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power-domain-names = "perf";
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l0>;
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};
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cpu1: cpu@100 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x100>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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power-domains = <&scmi_perf IMX94_PERF_A55>;
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power-domain-names = "perf";
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l1>;
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};
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cpu2: cpu@200 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x200>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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power-domains = <&scmi_perf IMX94_PERF_A55>;
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power-domain-names = "perf";
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l2>;
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};
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cpu3: cpu@300 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x300>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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power-domains = <&scmi_perf IMX94_PERF_A55>;
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power-domain-names = "perf";
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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i-cache-sets = <128>;
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d-cache-size = <32768>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l3>;
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};
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l2_cache_l0: l2-cache-l0 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l2_cache_l1: l2-cache-l1 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l2_cache_l2: l2-cache-l2 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l2_cache_l3: l2-cache-l3 {
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compatible = "cache";
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cache-size = <65536>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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l3_cache: l3-cache {
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compatible = "cache";
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cache-size = <1048576>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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