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f478e7ae18
Add overlay to support PHYTEC PEB-WLBT-07 WiFi/Bluetooth evaluation adapter on phyBOARD-Nash-i.MX93 board. Adapter uses the u-blox MAYA-W2 module (IW612 chipset) which is capable of Wi-Fi 6 and Bluetooth 5.4 LE. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
88 lines
2.2 KiB
Text
88 lines
2.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2025 PHYTEC Messtechnik GmbH
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* Author: Primoz Fiser <primoz.fiser@norik.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx93-pinfunc.h"
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&{/} {
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usdhc3_pwrseq: usdhc3-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
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};
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};
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&lpuart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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status = "okay";
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bluetooth {
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compatible = "nxp,88w8987-bt";
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};
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};
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/*
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* NOTE: When uSDHC3 port is multiplexed on GPIO_IO[27:22] pads, it only
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* supports 50 MHz mode, due to introduction of potential variations in
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* trace impedance, drive strength, and timing skew. Refer to i.MX 93
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* Application Processors Data Sheet, Rev. 3, page 60 for more details.
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*/
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&usdhc3 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wlbt>;
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pinctrl-1 = <&pinctrl_usdhc3_sleep>, <&pinctrl_wlbt>;
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mmc-pwrseq = <&usdhc3_pwrseq>;
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bus-width = <4>;
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keep-power-in-suspend;
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non-removable;
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wakeup-source;
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status = "okay";
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};
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&iomuxc {
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pinctrl_uart5: uart5grp {
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fsl,pins = <
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MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
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MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
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MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
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MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
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>;
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};
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/* need to config the SION for data and cmd pad, refer to ERR052021 */
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX93_PAD_GPIO_IO22__USDHC3_CLK 0x179e
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MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000178e
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MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
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MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
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MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
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MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e
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>;
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};
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pinctrl_usdhc3_sleep: usdhc3sleepgrp {
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fsl,pins = <
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MX93_PAD_GPIO_IO22__USDHC3_CLK 0x31e
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MX93_PAD_SD3_CMD__USDHC3_CMD 0x31e
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MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x31e
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MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x31e
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MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x31e
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MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x31e
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>;
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};
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pinctrl_wlbt: wlbtgrp {
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fsl,pins = <
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MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e /* WAKE_DEV */
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MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e /* WAKE_HOST */
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MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e /* PDn */
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>;
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};
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};
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