mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-18 22:14:16 +00:00
eed2d8e8d0
imx8-ss-vpu only contained imx8qxp IRQ numbers, only mu2_m0 uses the
correct imx8qm IRQ number, as imx8qxp lacks this MU.
Fix this by providing imx8qm IRQ numbers in the main imx8-ss-vpu.dtsi
and override the IRQ numbers in SoC-specific imx8qxp-ss-vpu.dtsi, similar
to reg property for VPU core devices.
Fixes: 0d9968d984 ("arm64: dts: freescale: imx8q: add imx vpu codec entries")
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
25 lines
443 B
Text
25 lines
443 B
Text
// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
|
|
/*
|
|
* Copyright 2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
|
|
* D-82229 Seefeld, Germany.
|
|
* Author: Alexander Stein
|
|
*/
|
|
|
|
&mu_m0 {
|
|
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&mu1_m0 {
|
|
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&vpu_core0 {
|
|
reg = <0x2d040000 0x10000>;
|
|
};
|
|
|
|
&vpu_core1 {
|
|
reg = <0x2d050000 0x10000>;
|
|
};
|
|
|
|
/delete-node/ &mu2_m0;
|
|
/delete-node/ &vpu_core2;
|