mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-31 23:27:20 +00:00
440bd77d25
Remove the gpio hog node which forces using DSI signals rather than the second LVDS channels signals. The dsi signals are not used in any of the current device trees. Leave that decision to the actual device tree which will also define the consumer of the signals. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
1308 lines
36 KiB
Text
1308 lines
36 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/* Copyright (C) 2025 Toradex */
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include "imx8mp.dtsi"
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/ {
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aliases {
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can0 = &flexcan2;
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can1 = &flexcan1;
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ethernet0 = &eqos;
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ethernet1 = &fec;
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mmc0 = &usdhc3;
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mmc1 = &usdhc2;
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mmc2 = &usdhc1;
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rtc0 = &rtc_i2c;
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rtc1 = &snvs_rtc;
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serial0 = &uart1;
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serial1 = &uart4;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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chosen {
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stdout-path = &uart4;
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};
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connector {
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compatible = "gpio-usb-b-connector", "usb-b-connector";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_id>;
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id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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label = "USB0";
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self-powered;
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type = "micro";
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vbus-supply = <®_usb0_vbus>;
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port {
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usb_dr_connector: endpoint {
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remote-endpoint = <&usb3_0_dwc>;
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sleep>;
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smarc_key_sleep: key-sleep {
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gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
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label = "SMARC_SLEEP#";
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wakeup-source;
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linux,code = <KEY_SLEEP>;
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};
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smarc_switch_lid: switch-lid {
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gpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>;
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label = "SMARC_LID#";
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linux,code = <SW_LID>;
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linux,input-type = <EV_SW>;
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};
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};
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reg_usb0_vbus: regulator-usb0-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_en_oc>;
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gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-name = "USB0_EN_OC#";
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};
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reg_usb1_vbus: regulator-usb1-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1_en_oc>;
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gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-name = "USB2_EN_OC#";
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};
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reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
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gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <100000>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "3V3_SD";
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startup-delay-us = <20000>;
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};
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reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
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compatible = "regulator-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2_vsel>;
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gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <1800000>;
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states = <1800000 0x1>,
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<3300000 0x0>;
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regulator-name = "PMIC_USDHC_VSELECT";
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vin-supply = <®_sd_3v3_1v8>;
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};
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reg_wifi_en: regulator-wifi-en {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wifi_pwr_en>;
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gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "CTRL_EN_WIFI";
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startup-delay-us = <2000>;
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};
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reserved-memory {
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linux,cma {
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size = <0 0x20000000>;
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alloc-ranges = <0 0x40000000 0 0x80000000>;
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};
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};
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sound_hdmi: sound-hdmi {
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compatible = "fsl,imx-audio-hdmi";
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model = "audio-hdmi";
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audio-cpu = <&aud2htx>;
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hdmi-out;
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status = "disabled";
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};
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};
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&A53_0 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_1 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_2 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_3 {
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cpu-supply = <®_vdd_arm>;
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};
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/* SMARC SPI0 */
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio4 28 GPIO_ACTIVE_LOW>;
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};
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/* SMARC SPI1 */
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_tpm_cs>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
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<&gpio4 3 GPIO_ACTIVE_LOW>,
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<&gpio3 6 GPIO_ACTIVE_LOW>;
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status = "okay";
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tpm@2 {
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compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
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reg = <2>;
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spi-max-frequency = <18500000>;
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};
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};
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/* SMARC GBE0 */
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>,
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<&pinctrl_eth_mdio>,
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<&pinctrl_eqos_1588_event>;
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phy-handle = <&eqos_phy>;
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phy-mode = "rgmii-id";
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snps,force_thresh_dma_mode;
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snps,mtl-rx-config = <&mtl_rx_setup>;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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mdio: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <5>;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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snps,map-to-dma-channel = <0>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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snps,map-to-dma-channel = <1>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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snps,map-to-dma-channel = <2>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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snps,map-to-dma-channel = <3>;
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};
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queue4 {
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snps,dcb-algorithm;
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snps,priority = <0xf0>;
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snps,map-to-dma-channel = <4>;
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};
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <5>;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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};
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queue4 {
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snps,dcb-algorithm;
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snps,priority = <0xf0>;
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};
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};
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};
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/* SMARC GBE1 */
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_1588_event>;
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phy-handle = <&fec_phy>;
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phy-mode = "rgmii-id";
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fsl,magic-packet;
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};
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/* SMARC CAN1 */
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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};
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/* SMARC CAN0 */
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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};
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&gpio1 {
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gpio-line-names = "SMARC_GPIO7", /* 0 */
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"SMARC_GPIO8",
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"",
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"PMIC_INT#",
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"PMIC_USDHC_VSELECT",
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"SMARC_GPIO9",
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"SMARC_GPIO10",
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"SMARC_GPIO11",
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"SMARC_GPIO12",
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"",
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"SMARC_GPIO5", /* 10 */
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"",
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"SMARC_USB0_EN_OC#",
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"SMARC_GPIO13",
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"SMARC_USB2_EN_OC#";
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};
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&gpio2 {
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gpio-line-names = "", /* 0 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"", /* 10 */
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"",
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"SMARC_SDIO_CD#",
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"",
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"",
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"",
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"",
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"",
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"",
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"SMARC_SDIO_PWR_EN",
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"SMARC_SDIO_WP"; /* 20 */
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};
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&gpio3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lvds_dsi_sel>;
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gpio-line-names = "ETH_0_INT#", /* 0 */
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"SLEEP#",
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"",
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"",
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"",
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"",
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"TPM_CS#",
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"LVDS_DSI_SEL",
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"MCU_INT#",
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"GPIO_EX_INT#",
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"", /* 10 */
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"",
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"",
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"",
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"",
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"",
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"SMARC_SMB_ALERT#",
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"",
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"",
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"",
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"SMARC_I2C_PM_DAT", /* 20 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"SMARC_I2C_PM_CK";
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};
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&gpio4 {
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gpio-line-names = "SMARC_PCIE_WAKE#", /* 0 */
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"",
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"",
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"SMARC_SPI1_CS1#",
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"",
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"",
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"",
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"",
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"",
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"",
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"", /* 10 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"SMARC_GPIO4",
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"SMARC_PCIE_A_RST#",
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"", /* 20 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"SMARC_SPI0_CS1#",
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"SMARC_GPIO6";
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};
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&gpio5 {
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gpio-line-names = "", /* 0 */
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"",
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"SMARC_USB0_OTG_ID",
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"SMARC_I2C_CAM1_CK",
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"SMARC_I2C_CAM1_DAT",
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"",
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"",
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"",
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"",
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"SMARC_SPI0_CS0#",
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"", /* 10 */
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"",
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"",
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"SMARC_SPI1_CS0#",
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"CTRL_I2C_SCL",
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"CTRL_I2C_SDA",
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"SMARC_I2C_LCD_CK",
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"SMARC_I2C_LCD_DAT",
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"SMARC_I2C_CAM0_CK",
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"SMARC_I2C_CAM0_DAT",
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"SMARC_I2C_GP_CK", /* 20 */
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"SMARC_I2C_GP_DAT";
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};
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/* SMARC HDMI */
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&hdmi_tx {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hdmi>;
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};
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/* On-module I2C */
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&i2c1 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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clock-frequency = <400000>;
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scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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single-master;
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status = "okay";
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som_gpio_expander: gpio@21 {
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compatible = "nxp,pcal6408";
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reg = <0x21>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcal6408>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gpio3>;
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interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-line-names =
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"SMARC_GPIO0",
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"SMARC_GPIO1",
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"SMARC_GPIO2",
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"SMARC_GPIO3",
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"SMARC_LCD0_VDD_EN",
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"SMARC_LCD0_BKLT_EN",
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"SMARC_LCD1_VDD_EN",
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"SMARC_LCD1_BKLT_EN";
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};
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pca9450: pmic@25 {
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compatible = "nxp,pca9450c";
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reg = <0x25>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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BUCK1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1000000>;
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regulator-min-microvolt = <805000>;
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regulator-name = "+VDD_SOC (PMIC BUCK1)";
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regulator-ramp-delay = <3125>;
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};
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reg_vdd_arm: BUCK2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1000000>;
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regulator-min-microvolt = <805000>;
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regulator-name = "+VDD_ARM (PMIC BUCK2)";
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regulator-ramp-delay = <3125>;
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nxp,dvs-run-voltage = <950000>;
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nxp,dvs-standby-voltage = <850000>;
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};
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reg_3v3: BUCK4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "+V3.3 (PMIC BUCK4)";
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};
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reg_1v8: BUCK5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "+V1.8 (PMIC BUCK5)";
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};
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BUCK6 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1155000>;
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regulator-min-microvolt = <1045000>;
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regulator-name = "+VDD_DDR (PMIC BUCK6)";
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};
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LDO1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1950000>;
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regulator-min-microvolt = <1710000>;
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regulator-name = "+V1.8_SNVS (PMIC LDO1)";
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};
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LDO3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "+V1.8A (PMIC LDO3)";
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};
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LDO4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "+V3.3_ADC (PMIC LDO4)";
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};
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reg_sd_3v3_1v8: LDO5 {
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regulator-max-microvolt = <3300000>;
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-name = "+V3.3_1.8_SD (PMIC LDO5)";
|
|
};
|
|
};
|
|
};
|
|
|
|
embedded-controller@28 {
|
|
compatible = "toradex,smarc-imx8mp-ec", "toradex,smarc-ec";
|
|
reg = <0x28>;
|
|
};
|
|
|
|
som_ec_gpio_expander: gpio@29 {
|
|
compatible = "toradex,ecgpiol16", "nxp,pcal6416";
|
|
reg = <0x29>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_mcu_int>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&gpio3>;
|
|
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-line-names =
|
|
"SMARC_CHARGER_PRSNT#",
|
|
"SMARC_CHARGING#",
|
|
"SMARC_LID#",
|
|
"SMARC_BATLOW#";
|
|
};
|
|
|
|
rtc_i2c: rtc@32 {
|
|
compatible = "epson,rx8130";
|
|
reg = <0x32>;
|
|
};
|
|
|
|
temperature-sensor@48 {
|
|
compatible = "ti,tmp1075";
|
|
reg = <0x48>;
|
|
};
|
|
|
|
eeprom@50 {
|
|
compatible = "st,24c02", "atmel,24c02";
|
|
reg = <0x50>;
|
|
pagesize = <16>;
|
|
};
|
|
};
|
|
|
|
/* SMARC I2C_LCD */
|
|
&i2c2 {
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
|
clock-frequency = <100000>;
|
|
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
single-master;
|
|
};
|
|
|
|
/* SMARC I2C_CAM0 */
|
|
&i2c3 {
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
pinctrl-1 = <&pinctrl_i2c3_gpio>;
|
|
clock-frequency = <400000>;
|
|
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
single-master;
|
|
};
|
|
|
|
/* SMARC I2C_GP */
|
|
&i2c4 {
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c4>;
|
|
pinctrl-1 = <&pinctrl_i2c4_gpio>;
|
|
clock-frequency = <400000>;
|
|
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
single-master;
|
|
status = "okay";
|
|
|
|
eeprom@50 {
|
|
compatible = "st,24c32", "atmel,24c32";
|
|
reg = <0x50>;
|
|
pagesize = <32>;
|
|
};
|
|
};
|
|
|
|
/* SMARC I2C_CAM1 */
|
|
&i2c5 {
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c5>;
|
|
pinctrl-1 = <&pinctrl_i2c5_gpio>;
|
|
clock-frequency = <400000>;
|
|
scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
single-master;
|
|
};
|
|
|
|
/* SMARC I2C_PM */
|
|
&i2c6 {
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c6>;
|
|
pinctrl-1 = <&pinctrl_i2c6_gpio>;
|
|
clock-frequency = <400000>;
|
|
scl-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
single-master;
|
|
};
|
|
|
|
&mdio {
|
|
eqos_phy: ethernet-phy@1 {
|
|
reg = <1>;
|
|
interrupt-parent = <&gpio3>;
|
|
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
};
|
|
|
|
fec_phy: ethernet-phy@2 {
|
|
reg = <2>;
|
|
interrupt-parent = <&gpio3>;
|
|
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
};
|
|
};
|
|
|
|
/* SMARC PCIE_A */
|
|
&pcie {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pcie>;
|
|
reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
&pcie_phy {
|
|
clocks = <&hsio_blk_ctrl>;
|
|
clock-names = "ref";
|
|
fsl,clkreq-unsupported;
|
|
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
|
|
};
|
|
|
|
/* SMARC LCD1_BKLT_PWM */
|
|
&pwm1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_lcd1_bklt_pwm1>;
|
|
};
|
|
|
|
/* SMARC LCD0_BKLT_PWM */
|
|
&pwm2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_lcd0_bklt_pwm2>;
|
|
};
|
|
|
|
/* SMARC GPIO5 as PWM */
|
|
&pwm3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_gpio5_pwm>;
|
|
};
|
|
|
|
&snvs_pwrkey {
|
|
status = "okay";
|
|
};
|
|
|
|
/* SMARC SER0 */
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
uart-has-rtscts;
|
|
};
|
|
|
|
/* SMARC SER2 */
|
|
&uart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
uart-has-rtscts;
|
|
};
|
|
|
|
/* On-module Bluetooth, optional SMARC SER3 */
|
|
&uart3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_bt_uart>;
|
|
uart-has-rtscts;
|
|
status = "okay";
|
|
|
|
som_bt: bluetooth {
|
|
compatible = "mrvl,88w8997";
|
|
max-speed = <921600>;
|
|
};
|
|
};
|
|
|
|
/* SMARC SER1, used as the Linux Console */
|
|
&uart4 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart4>;
|
|
};
|
|
|
|
/* SMARC USB0 */
|
|
&usb3_0 {
|
|
fsl,disable-port-power-control;
|
|
};
|
|
|
|
/* SMARC USB1..4 */
|
|
&usb3_1 {
|
|
fsl,disable-port-power-control;
|
|
};
|
|
|
|
&usb3_phy1 {
|
|
vbus-supply = <®_usb1_vbus>;
|
|
};
|
|
|
|
&usb_dwc3_0 {
|
|
adp-disable;
|
|
dr_mode = "otg";
|
|
hnp-disable;
|
|
maximum-speed = "high-speed";
|
|
srp-disable;
|
|
usb-role-switch;
|
|
|
|
port {
|
|
usb3_0_dwc: endpoint {
|
|
remote-endpoint = <&usb_dr_connector>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb_dwc3_1 {
|
|
dr_mode = "host";
|
|
};
|
|
|
|
/* On-module Wi-Fi */
|
|
&usdhc1 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
|
keep-power-in-suspend;
|
|
non-removable;
|
|
vmmc-supply = <®_wifi_en>;
|
|
status = "okay";
|
|
};
|
|
|
|
/* SMARC SDIO */
|
|
&usdhc2 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
|
pinctrl-0 = <&pinctrl_usdhc2>,
|
|
<&pinctrl_usdhc2_cd>,
|
|
<&pinctrl_usdhc2_wp>;
|
|
pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
|
|
<&pinctrl_usdhc2_cd>,
|
|
<&pinctrl_usdhc2_wp>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
|
|
<&pinctrl_usdhc2_cd>,
|
|
<&pinctrl_usdhc2_wp>;
|
|
pinctrl-3 = <&pinctrl_usdhc2_sleep>,
|
|
<&pinctrl_usdhc2_cd_sleep>,
|
|
<&pinctrl_usdhc2_wp>;
|
|
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
|
|
assigned-clock-rates = <400000000>;
|
|
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
|
vmmc-supply = <®_usdhc2_vmmc>;
|
|
vqmmc-supply = <®_usdhc2_vqmmc>;
|
|
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
/* On-module eMMC */
|
|
&usdhc3 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
|
|
assigned-clock-rates = <400000000>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
/* On-module Bluetooth */
|
|
pinctrl_bt_uart: btuartgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x1c4>, /* WiFi_UART_TXD */
|
|
<MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x1c4>, /* WiFi_UART_RXD */
|
|
<MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x1c4>, /* WiFi_UART_RTS */
|
|
<MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x1c4>; /* WiFi_UART_CTS */
|
|
};
|
|
|
|
/* SMARC CAM_MCK */
|
|
pinctrl_csi_mclk: csimclkgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x16>; /* SMARC S6 - CAM_MCK */
|
|
};
|
|
|
|
/* SMARC SPI0 */
|
|
pinctrl_ecspi1: ecspi1grp {
|
|
fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SMARC P45 - SPI0_DIN */
|
|
<MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SMARC P46 - SPI0_DO */
|
|
<MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SMARC P44 - SPI0_CK */
|
|
<MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>, /* SMARC P43 - SPI0_CS0# */
|
|
<MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SMARC P31 - SPI0_CS1# */
|
|
};
|
|
|
|
/* SMARC SPI1 */
|
|
pinctrl_ecspi2: ecspi2grp {
|
|
fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c4>, /* SMARC P56 - SPI1_DIN */
|
|
<MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x4>, /* SMARC P57 - SPI1_DO */
|
|
<MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x4>, /* SMARC P58 - SPI1_CK */
|
|
<MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>, /* SMARC P54 - SPI1_CS0# */
|
|
<MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c4>; /* SMARC P55 - SPI1_CS1# */
|
|
};
|
|
|
|
/* ETH_0 RGMII (On-module PHY) */
|
|
pinctrl_eqos: eqosgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, /* ETH0_RGMII_RXD0 */
|
|
<MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, /* ETH0_RGMII_RXD1 */
|
|
<MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, /* ETH0_RGMII_RXD2 */
|
|
<MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, /* ETH0_RGMII_RXD3 */
|
|
<MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, /* ETH0_RGMII_RXC */
|
|
<MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, /* ETH0_RGMII_RX_CTL */
|
|
<MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16>, /* ETH0_RGMII_TXD0 */
|
|
<MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16>, /* ETH0_RGMII_TXD1 */
|
|
<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16>, /* ETH0_RGMII_TXD2 */
|
|
<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16>, /* ETH0_RGMII_TXD3 */
|
|
<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16>, /* ETH0_RGMII_TX_CTL */
|
|
<MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16>; /* ETH0_RGMII_TXC */
|
|
};
|
|
|
|
/* SMARC GBE0_SDP */
|
|
pinctrl_eqos_1588_event: eqos1588eventgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x4>; /* SMARC P6 - GBE0_SDP */
|
|
};
|
|
|
|
/* ETH_0_MDIO and ETH_0_INT# shared between ETH_PHY0 and ETH_PHY1 */
|
|
pinctrl_eth_mdio: ethmdiogrp {
|
|
fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2>, /* ETH_0_MDC */
|
|
<MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2>, /* ETH_0_MDIO */
|
|
<MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x80>; /* ETH_0_INT# */
|
|
};
|
|
|
|
/* ETH_1 RGMII (On-module PHY) */
|
|
pinctrl_fec: fecgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, /* ETH1_RGMII_RXD0 */
|
|
<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, /* ETH1_RGMII_RXD1 */
|
|
<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, /* ETH1_RGMII_RXD2 */
|
|
<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, /* ETH1_RGMII_RXD3 */
|
|
<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, /* ETH1_RGMII_RXC */
|
|
<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, /* ETH1_RGMII_RX_CTL */
|
|
<MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16>, /* ETH1_RGMII_TXD0 */
|
|
<MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16>, /* ETH1_RGMII_TXD1 */
|
|
<MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16>, /* ETH1_RGMII_TXD2 */
|
|
<MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16>, /* ETH1_RGMII_TXD3 */
|
|
<MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16>, /* ETH1_RGMII_TX_CTL */
|
|
<MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16>; /* ETH1_RGMII_TXC */
|
|
};
|
|
|
|
/* SMARC GBE1_SDP */
|
|
pinctrl_fec_1588_event: fec1588eventgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x4>; /* SMARC P5 - GBE1_SDP */
|
|
};
|
|
|
|
/* SMARC CAN1 */
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154>, /* SMARC P146 - CAN1_RX */
|
|
<MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154>; /* SMARC P145 - CAN1_TX */
|
|
};
|
|
|
|
/* SMARC CAN0 */
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SMARC P144 - CAN0_RX */
|
|
<MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SMARC P143 - CAN0_TX */
|
|
};
|
|
|
|
/* SMARC GPIO4 */
|
|
pinctrl_gpio4: gpio4grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x144>; /* SMARC P112 - GPIO4 */
|
|
};
|
|
|
|
/* SMARC GPIO5 */
|
|
pinctrl_gpio5: gpio5grp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x144>; /* SMARC P113 - GPIO5 */
|
|
};
|
|
|
|
/* SMARC GPIO5 as PWM */
|
|
pinctrl_gpio5_pwm: gpio5pwmgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x12>; /* SMARC P113 - PWM_OUT */
|
|
};
|
|
|
|
/* SMARC GPIO6 */
|
|
pinctrl_gpio6: gpio6grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x144>; /* SMARC P114 - GPIO6 */
|
|
};
|
|
|
|
/* SMARC GPIO7 */
|
|
pinctrl_gpio7: gpio7grp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x144>; /* SMARC P115 - GPIO7 */
|
|
};
|
|
|
|
/* SMARC GPIO8 */
|
|
pinctrl_gpio8: gpio8grp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x144>; /* SMARC P116 - GPIO8 */
|
|
};
|
|
|
|
/* SMARC GPIO9 */
|
|
pinctrl_gpio9: gpio9grp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x144>; /* SMARC P117 - GPIO9 */
|
|
};
|
|
|
|
/* SMARC GPIO10 */
|
|
pinctrl_gpio10: gpio10grp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x144>; /* SMARC P118 - GPIO10 */
|
|
};
|
|
|
|
/* SMARC GPIO11 */
|
|
pinctrl_gpio11: gpio11grp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x144>; /* SMARC P119 - GPIO11 */
|
|
};
|
|
|
|
/* SMARC GPIO12 */
|
|
pinctrl_gpio12: gpio12grp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x144>; /* SMARC S142 - GPIO12 */
|
|
};
|
|
|
|
/* SMARC GPIO13 */
|
|
pinctrl_gpio13: gpio13grp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144>; /* SMARC S123 - GPIO13 */
|
|
};
|
|
|
|
/* SMARC HDMI */
|
|
pinctrl_hdmi: hdmigrp {
|
|
fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c6>, /* SMARC P105 - HDMI_CTRL_CK */
|
|
<MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c6>, /* SMARC P106 - HDMI_CTRL_DAT */
|
|
<MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x180>; /* SMARC P104 - HDMI_HPD */
|
|
};
|
|
|
|
/* On-module I2C */
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* CTRL_I2C_SCL */
|
|
<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* CTRL_I2C_SDA */
|
|
};
|
|
|
|
/* On-module I2C as GPIOs */
|
|
pinctrl_i2c1_gpio: i2c1gpiogrp {
|
|
fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* CTRL_I2C_SCL */
|
|
<MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* CTRL_I2C_SDA */
|
|
};
|
|
|
|
/* SMARC I2C_LCD */
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */
|
|
<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */
|
|
};
|
|
|
|
/* SMARC I2C_LCD as GPIOs */
|
|
pinctrl_i2c2_gpio: i2c2gpiogrp {
|
|
fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */
|
|
<MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */
|
|
};
|
|
|
|
/* SMARC I2C_CAM0 */
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */
|
|
<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */
|
|
};
|
|
|
|
/* SMARC I2C_CAM0 as GPIOs */
|
|
pinctrl_i2c3_gpio: i2c3gpiogrp {
|
|
fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */
|
|
<MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */
|
|
};
|
|
|
|
/* SMARC I2C_GP */
|
|
pinctrl_i2c4: i2c4grp {
|
|
fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SMARC S48 - I2C_GP_CK */
|
|
<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */
|
|
};
|
|
|
|
/* SMARC I2C_GP as GPIOs */
|
|
pinctrl_i2c4_gpio: i2c4gpiogrp {
|
|
fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SMARC S48 - I2C_GP_CK */
|
|
<MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */
|
|
};
|
|
|
|
/* SMARC I2C_CAM1 */
|
|
pinctrl_i2c5: i2c5grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */
|
|
<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */
|
|
};
|
|
|
|
/* SMARC I2C_CAM1 as GPIOs */
|
|
pinctrl_i2c5_gpio: i2c5gpiogrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */
|
|
<MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */
|
|
};
|
|
|
|
/* SMARC I2C_PM */
|
|
pinctrl_i2c6: i2c6grp {
|
|
fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x400001c6>, /* SMARC P121 - I2C_PM_CK */
|
|
<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */
|
|
};
|
|
|
|
/* SMARC I2C_PM as GPIOs */
|
|
pinctrl_i2c6_gpio: i2c6gpiogrp {
|
|
fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x400001c6>, /* SMARC P121 - I2C_PM_CK */
|
|
<MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */
|
|
};
|
|
|
|
pinctrl_lvds_dsi_sel: lvdsdsiselgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x104>; /* LVDS_DSI_SEL */
|
|
};
|
|
|
|
pinctrl_mcu_int: mcuintgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1C0>; /* MCU_INT# */
|
|
};
|
|
|
|
/* SMARC LCD1_BKLT_PWM */
|
|
pinctrl_lcd1_bklt_pwm1: pwm1grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x12>; /* SMARC S122 - LCD1_BKLT_PWM */
|
|
};
|
|
|
|
/* SMARC LCD0_BKLT_PWM */
|
|
pinctrl_lcd0_bklt_pwm2: pwm2grp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x12>; /* SMARC S141 - LCD0_BKLT_PWM */
|
|
};
|
|
|
|
/* PCAL6408 Interrupt */
|
|
pinctrl_pcal6408: pcal6408intgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x1c4>; /* GPIO_EX_INT# */
|
|
};
|
|
|
|
/* SMARC PCIE_A */
|
|
pinctrl_pcie: pciegrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c0>, /* SMARC S146 - PCIE_WAKE# */
|
|
<MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x04>; /* SMARC P75 - PCIE_A_RST# */
|
|
};
|
|
|
|
/* PMIC Interrupt */
|
|
pinctrl_pmic: pmicintgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
|
|
};
|
|
|
|
/* SMARC I2S0 */
|
|
pinctrl_sai1: sai1grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x94>, /* SMARC S42 - I2S0_CK */
|
|
<MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x94>, /* SMARC S39 - I2S0_LRCLK */
|
|
<MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x94>, /* SMARC S41 - I2S0_SDIN */
|
|
<MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x94>; /* SMARC S40 - I2S0_SDOUT */
|
|
};
|
|
|
|
/* SMARC AUDIO_MCK */
|
|
pinctrl_sai1_mclk: sai1mclkgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>; /* SMARC S38 - AUDIO_MCK */
|
|
};
|
|
|
|
/* SMARC I2S2 */
|
|
pinctrl_sai3: sai3grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94>, /* SMARC S52 - I2S2_SDIN */
|
|
<MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94>, /* SMARC S53 - I2S2_CK */
|
|
<MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94>, /* SMARC S51 - I2S2_SDOUT */
|
|
<MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94>; /* SMARC S50 - I2S2_LRCLK */
|
|
};
|
|
|
|
/* SMARC SLEEP# */
|
|
pinctrl_sleep: sleepgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */
|
|
};
|
|
|
|
/* SMARC SMB_ALERT# */
|
|
pinctrl_smb_alert: smbalertgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1C0>; /* SMARC P1 - SMB_ALERT# */
|
|
};
|
|
|
|
/* TPM_CS# */
|
|
pinctrl_tpm_cs: tpmcsgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x82>; /* TPM_CS# */
|
|
};
|
|
|
|
/* WIFI_BT_WKUP_HOST/TPM_INT# */
|
|
pinctrl_tpm_irq_wifi_bt_wkup: tpmirq-wifibtwkupgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x16>; /* WIFI_BT_WKUP_HOST/TPM_INT# */
|
|
};
|
|
|
|
/* SMARC SER0 */
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SMARC P132 - SER2_CTS */
|
|
<MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SMARC P131 - SER2_RTS */
|
|
<MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SMARC P130 - SER2_RX */
|
|
<MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SMARC P139 - SER2_TX */
|
|
};
|
|
|
|
/* SMARC SER2 */
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SMARC P139 - SER2_CTS */
|
|
<MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SMARC P138 - SER2_RTS */
|
|
<MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SMARC P137 - SER2_RX */
|
|
<MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SMARC P136 - SER2_TX */
|
|
};
|
|
|
|
/* SMARC SER3 */
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SMARC P141 - SER3_RX */
|
|
<MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SMARC P140 - SER3_TX */
|
|
};
|
|
|
|
/* SMARC SER1 */
|
|
pinctrl_uart4: uart4grp {
|
|
fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SMARC P135 - SER1_RX */
|
|
<MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SMARC P134 - SER1_TX */
|
|
};
|
|
|
|
/* SMARC USB0_OTG_ID */
|
|
pinctrl_usb0_id: usb0idgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SMARC P64 - USB0_OTG_ID */
|
|
};
|
|
|
|
/* SMARC USB0_EN_OC# */
|
|
pinctrl_usb0_en_oc: usb0enocgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x04>; /* SMARC P62 - USB0_EN_OC# */
|
|
};
|
|
|
|
/* On module USB Hub VBUS, or SMARC USB2_EN_OC# depending on assembling */
|
|
pinctrl_usb1_en_oc: usb1enocgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04>; /* SMARC P71 - USB2_EN_OC# */
|
|
};
|
|
|
|
/* On-module Wi-Fi */
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, /* WiFi_SDIO_CLK */
|
|
<MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, /* WiFi_SDIO_CMD */
|
|
<MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, /* WiFi_SDIO_DATA0 */
|
|
<MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, /* WiFi_SDIO_DATA1 */
|
|
<MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, /* WiFi_SDIO_DATA2 */
|
|
<MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; /* WiFi_SDIO_DATA3 */
|
|
};
|
|
|
|
/* On-module Wi-Fi */
|
|
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, /* WiFi_SDIO_CLK */
|
|
<MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, /* WiFi_SDIO_CMD */
|
|
<MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, /* WiFi_SDIO_DATA0 */
|
|
<MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, /* WiFi_SDIO_DATA1 */
|
|
<MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, /* WiFi_SDIO_DATA2 */
|
|
<MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; /* WiFi_SDIO_DATA3 */
|
|
};
|
|
|
|
/* On-module Wi-Fi */
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, /* WiFi_SDIO_CLK */
|
|
<MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, /* WiFi_SDIO_CMD */
|
|
<MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, /* WiFi_SDIO_DATA0 */
|
|
<MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, /* WiFi_SDIO_DATA1 */
|
|
<MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, /* WiFi_SDIO_DATA2 */
|
|
<MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; /* WiFi_SDIO_DATA3 */
|
|
};
|
|
|
|
/* SMARC SDIO */
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SMARC P36 - SDIO_CK */
|
|
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SMARC P34 - SDIO_CMD */
|
|
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SMARC P39 - SDIO_DO */
|
|
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SMARC P40 - SDIO_D1 */
|
|
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SMARC P41 - SDIO_D2 */
|
|
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SMARC P42 - SDIO_D3 */
|
|
};
|
|
|
|
/* SMARC SDIO 100MHz */
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, /* SMARC P36 - SDIO_CK */
|
|
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, /* SMARC P34 - SDIO_CMD */
|
|
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, /* SMARC P39 - SDIO_DO */
|
|
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, /* SMARC P40 - SDIO_D1 */
|
|
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, /* SMARC P41 - SDIO_D2 */
|
|
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; /* SMARC P42 - SDIO_D3 */
|
|
};
|
|
|
|
/* SMARC SDIO 200MHz */
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, /* SMARC P36 - SDIO_CK */
|
|
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, /* SMARC P34 - SDIO_CMD */
|
|
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, /* SMARC P39 - SDIO_DO */
|
|
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, /* SMARC P40 - SDIO_D1 */
|
|
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, /* SMARC P41 - SDIO_D2 */
|
|
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; /* SMARC P42 - SDIO_D3 */
|
|
};
|
|
|
|
/* SMARC SDIO_CD# */
|
|
pinctrl_usdhc2_cd: usdhc2cdgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SMARC P35 - SDIO_CD# */
|
|
};
|
|
|
|
/* SMARC SDIO_CD# */
|
|
pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SMARC P35 - SDIO_CD# */
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};
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/* SMARC SDIO_PWR_EN */
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pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
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fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* SMARC P37 - SDIO_PWR_EN */
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};
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/* SMARC SDIO Sleep - Avoid backfeeding with removed card power */
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pinctrl_usdhc2_sleep: usdhc2slpgrp {
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fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, /* SMARC P36 - SDIO_CK */
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<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, /* SMARC P34 - SDIO_CMD */
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<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, /* SMARC P39 - SDIO_DO */
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<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, /* SMARC P39 - SDIO_D1 */
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<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, /* SMARC P39 - SDIO_D2 */
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<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; /* SMARC P39 - SDIO_D3 */
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};
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pinctrl_usdhc2_vsel: usdhc2vselgrp {
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fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x4>; /* PMIC_USDHC_VSELECT */
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};
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/* SMARC SDIO_WP */
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pinctrl_usdhc2_wp: usdhc2wpgrp {
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fsl,pins = <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x144>; /* SMARC P33 - SDIO_WP */
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};
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/* On-module eMMC */
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, /* eMMC_STROBE */
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<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, /* eMMC_DATA5 */
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<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, /* eMMC_DATA6 */
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<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, /* eMMC_DATA7 */
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<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, /* eMMC_DATA0 */
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<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, /* eMMC_DATA1 */
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<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, /* eMMC_DATA2 */
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<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, /* eMMC_DATA3 */
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<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, /* eMMC_DATA4 */
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|
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, /* eMMC_CLK */
|
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<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; /* eMMC_CMD */
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|
};
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|
|
|
/* On-module eMMC */
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, /* eMMC_STROBE */
|
|
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, /* eMMC_DATA5 */
|
|
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, /* eMMC_DATA6 */
|
|
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, /* eMMC_DATA7 */
|
|
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, /* eMMC_DATA0 */
|
|
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, /* eMMC_DATA1 */
|
|
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, /* eMMC_DATA2 */
|
|
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, /* eMMC_DATA3 */
|
|
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, /* eMMC_DATA4 */
|
|
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, /* eMMC_CLK */
|
|
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; /* eMMC_CMD */
|
|
};
|
|
|
|
/* On-module eMMC */
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, /* eMMC_STROBE */
|
|
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, /* eMMC_DATA5 */
|
|
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, /* eMMC_DATA6 */
|
|
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, /* eMMC_DATA7 */
|
|
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, /* eMMC_DATA0 */
|
|
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, /* eMMC_DATA1 */
|
|
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, /* eMMC_DATA2 */
|
|
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, /* eMMC_DATA3 */
|
|
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, /* eMMC_DATA4 */
|
|
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, /* eMMC_CLK */
|
|
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; /* eMMC_CMD */
|
|
};
|
|
|
|
/* SoC Watchdog */
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x4>; /* CTRL_SOC_WDOG */
|
|
};
|
|
|
|
/* On-module Wi-Fi power enable */
|
|
pinctrl_wifi_pwr_en: wifipwrengrp {
|
|
fsl,pins = <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x104>; /* CTRL_EN_WIFI */
|
|
};
|
|
};
|